The address of CSR instreth register bug

[mvlamar]

Hi,
According to Table 2.2 on page 9 of the manual riscv-privilegied-v1.10, the CSR instreth register has the address 0xC82, ie 3202, not 3201, as defined in the Rars.
Is there any plan to implement time and timeh registers?

[]
Marcus Vinicius

[TheThirdOne]

You are absolutely right and I have pushed the fix.

As for time and timeh, there is some discussion of them in #3 and @zacharyselk ended up making a tool to handle a MMIO time register and interrupts.

The gist of why the time CSR is not implemented is that just assigning it from system time seems like it might lead to problems when interactively debugging a program. So I decided to leave it unimplemented at least until I had a few community who might have an opinion on what behavior it should have.

I am certainly open to implementing those CSRs if you think that a direct mapping from system time is a good solution.

[mvlamar]

I agree.