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device configuration tuning
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@thotro
thotro committed May 18, 2015
1 parent cf14239 commit 0ee5718
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Showing 3 changed files with 116 additions and 15 deletions.
9 changes: 7 additions & 2 deletions DW1000-arduino-test/DW1000-arduino-receiver-test/DW1000-arduino-receiver-test.ino
View file
Expand Up @@ -63,7 +63,7 @@ void serviceIRQ() {
numReceived++;
}

void loop() {
void loop() {
// TODO proper sender config and receiver test
// Interrupt version of transmit: Confirmation of ISR status change
if(received) {
Expand All @@ -76,7 +76,12 @@ void loop() {
dw.startReceive();
}
// wait a bit
delay(100);
delay(1000);
//Serial.println(dw.getPrettyBytes(SYS_STATUS, LEN_SYS_STATUS));
//Serial.println(dw.getPrettyBytes(CHAN_CTRL, LEN_CHAN_CTRL));

// TODO re-issue receive after error
dw.newReceive();
dw.setDefaults();
dw.startReceive();
}
69 changes: 60 additions & 9 deletions DW1000/DW1000.cpp
View file
Expand Up @@ -58,15 +58,51 @@ void DW1000::initialize() {
clearInterrupts();
writeSystemEventMaskRegister();
// tell the chip to load the LDE microcode
byte pmscctrl0[LEN_PMSC_CTRL0];
byte otpctrl[LEN_OTP_CTRL];
readBytes(OTP_CTRL, OTP_CTRL_SUB, otpctrl, LEN_OTP_CTRL);
setBit(otpctrl, LEN_OTP_CTRL, LDELOAD_BIT, true);
memset(otpctrl, 0x8000, LEN_OTP_CTRL);
memset(pmscctrl0, 0x0301, LEN_PMSC_CTRL0);
writeBytes(PMSC_CTRL0, NO_SUB, pmscctrl0, LEN_PMSC_CTRL0);
writeBytes(OTP_CTRL, OTP_CTRL_SUB, otpctrl, LEN_OTP_CTRL);
delay(10);
memset(pmscctrl0, 0x0200, LEN_PMSC_CTRL0);
writeBytes(PMSC_CTRL0, NO_SUB, pmscctrl0, LEN_PMSC_CTRL0);
tune();
delay(10);
}

void DW1000::tune() {
// re-tune chip for channel 5 (default)
byte agctune1[LEN_AGC_TUNE1];
byte agctune2[LEN_AGC_TUNE2];
byte drxtune2[LEN_DRX_TUNE2];
byte ldecfg1[LEN_LDE_CFG1];
byte ldecfg2[LEN_LDE_CFG2];
byte txpower[LEN_TX_POWER];
byte rftxctrl[LEN_RF_TXCTRL];
byte tcpgdelay[LEN_TC_PGDELAY];
byte fsplltune[LEN_FS_PLLTUNE];
memset(agctune1, 0x8870, LEN_AGC_TUNE1);
memset(agctune2, 0x2502A907, LEN_AGC_TUNE2);
writeBytes(AGC_TUNE2, AGC_TUNE2_SUB, agctune2, LEN_AGC_TUNE2);
// TODO others as well, see 2.5.5, p. 21
memset(drxtune2, 0x311A002D, LEN_DRX_TUNE2);
memset(ldecfg1, 0x6D, LEN_LDE_CFG1);
memset(ldecfg2, 0x1607, LEN_LDE_CFG2);
memset(txpower, 0x0E082848, LEN_TX_POWER);
memset(rftxctrl, 0x001E3FE0, LEN_RF_TXCTRL);
memset(tcpgdelay, 0xC0, LEN_TC_PGDELAY);
memset(fsplltune, 0xA6, LEN_FS_PLLTUNE);
writeBytes(AGC_TUNE, AGC_TUNE1_SUB, agctune1, LEN_AGC_TUNE1);
writeBytes(AGC_TUNE, AGC_TUNE2_SUB, agctune2, LEN_AGC_TUNE2);
writeBytes(DRX_TUNE, DRX_TUNE2_SUB, drxtune2, LEN_DRX_TUNE2);
writeBytes(LDE_CFG, LDE_CFG1_SUB, ldecfg1, LEN_LDE_CFG1);
writeBytes(LDE_CFG, LDE_CFG2_SUB, ldecfg2, LEN_LDE_CFG2);
writeBytes(TX_POWER, NO_SUB, txpower, LEN_TX_POWER);
writeBytes(RF_CONF, RF_TXCTRL_SUB, rftxctrl, LEN_RF_TXCTRL);
writeBytes(TX_CAL, TC_PGDELAY_SUB, tcpgdelay, LEN_TC_PGDELAY);
writeBytes(FS_CTRL, FS_PLLTUNE_SUB, fsplltune, LEN_FS_PLLTUNE);

// TODO others as well, RF_TXCTRL, TX_PGDELAY, FS_PLLTUNE, LDOTUNE
// TODO see 2.5.5, p. 21
}

/* ###########################################################################
Expand Down Expand Up @@ -181,6 +217,10 @@ void DW1000::interruptOnReceived(boolean val) {
setBit(_sysmask, LEN_SYS_MASK, RXDFR_BIT, val);
}

void DW1000::interruptOnAutomaticAcknowledgeTrigger(boolean val) {
setBit(_sysmask, LEN_SYS_MASK, AAT_BIT, val);
}

void DW1000::clearInterrupts() {
memset(_sysmask, 0, LEN_SYS_MASK);
}
Expand Down Expand Up @@ -253,6 +293,16 @@ void DW1000::pulseFrequency(byte freq) {
}
_txfctrl[2] |= (byte)(freq & 0xFF);
_chanctrl[2] |= (byte)((freq << 2) & 0xFF);
// tuning
byte agctune1[LEN_AGC_TUNE1];
if(freq == TX_PULSE_FREQ_16MHZ) {
memset(agctune1, 0x8870, LEN_AGC_TUNE1);
} else if(freq == TX_PULSE_FREQ_64MHZ) {
memset(agctune1, 0x889B, LEN_AGC_TUNE1);
} else {
return;
}
writeBytes(AGC_TUNE, AGC_TUNE1_SUB, agctune1, LEN_AGC_TUNE1);
}

void DW1000::preambleLength(byte prealen) {
Expand All @@ -270,8 +320,8 @@ void DW1000::extendedFrameLength(boolean val) {
}

void DW1000::newReceive() {
clearReceiveStatus();
memset(_sysctrl, 0, LEN_SYS_CTRL);
clearReceiveStatus();
_deviceMode = RX_MODE;
}

Expand All @@ -281,8 +331,8 @@ void DW1000::startReceive() {
}

void DW1000::newTransmit() {
clearTransmitStatus();
memset(_sysctrl, 0, LEN_SYS_CTRL);
clearTransmitStatus();
_deviceMode = TX_MODE;
}

Expand All @@ -294,18 +344,19 @@ void DW1000::setDefaults() {
suppressFrameCheck(false);
extendedFrameLength(false);
} else if(_deviceMode == IDLE_MODE) {
dataRate(TRX_RATE_6800KBPS);
/*dataRate(TRX_RATE_6800KBPS);
pulseFrequency(TX_PULSE_FREQ_16MHZ);
preambleLength(TX_PREAMBLE_LEN_1024);
setReceiverAutoReenable(true);
setReceiverAutoReenable(true);*/
interruptOnAutomaticAcknowledgeTrigger(true);
}
}

void DW1000::startTransmit() {
// set transmit flag
setBit(_sysctrl, LEN_SYS_CTRL, TXSTRT_BIT, true);
writeBytes(SYS_CTRL, NO_SUB, _sysctrl, LEN_SYS_CTRL);
// reset to idel
// reset to idle
_deviceMode = IDLE_MODE;
}

Expand Down
53 changes: 49 additions & 4 deletions DW1000/DW1000.h
View file
Expand Up @@ -58,6 +58,7 @@
// system event status register
#define SYS_STATUS 0x0F
#define LEN_SYS_STATUS 5
#define AAT_BIT 3
#define TXFRB_BIT 4
#define TXPRS_BIT 5
#define TXPHS_BIT 6
Expand Down Expand Up @@ -106,17 +107,59 @@
#define CHAN_CTRL 0x1F
#define LEN_CHAN_CTRL 4

// OTP control
// OTP control (for LDE micro code loading only)
#define OTP_CTRL 0x2D
#define OTP_CTRL_SUB 0x06
#define LEN_OTP_CTRL 2
#define LDELOAD_BIT 15

// AGC_TUNE2 (for re-tuning only)
#define AGC_TUNE2 0x23
// PMSC_CTRL0 (for LDE micro code loading only)
#define PMSC_CTRL0 0x36
#define LEN_PMSC_CTRL0 2

// AGC_TUNE1/2 (for re-tuning only)
// TODO AGC_TUNE1 needs to be adjusted with PRF (see Table 22)
#define AGC_TUNE 0x23
#define AGC_TUNE1_SUB 0x04
#define AGC_TUNE2_SUB 0x0C
#define LEN_AGC_TUNE1 2
#define LEN_AGC_TUNE2 4

// DRX_TUNE2 (for re-tuning only)
// TODO needs to be adjusted with preamble len and PRF (see Table 31)
#define DRX_TUNE 0x27
#define DRX_TUNE2_SUB 0x08
#define LEN_DRX_TUNE2 4

// LDE_CFG1 (for re-tuning only)
// TODO LDE_CFG2 needs to be adjusted with PRF (see Table 47)
#define LDE_CFG 0x2E
#define LDE_CFG1_SUB 0x0806
#define LDE_CFG2_SUB 0x1806
#define LEN_LDE_CFG1 1
#define LEN_LDE_CFG2 2

// TX_POWER (for re-tuning only)
#define TX_POWER 0x1E
#define LEN_TX_POWER 4

// RF_CONF (for re-tuning only)
// TODO RX_TXCTRL needs to be adjusted with channel (see Table 35)
#define RF_CONF 0x28
#define RF_TXCTRL_SUB 0x0C
#define LEN_RF_TXCTRL 4

// TX_CAL (for re-tuning only)
// TODO TC_PGDELAY needs to be adjusted with channel (see Table 37)
#define TX_CAL 0x2A
#define TC_PGDELAY_SUB 0x0B
#define LEN_TC_PGDELAY 1

// FS_CTRL (for re-tuning only)
// TODO FS_PLLTUNE needs to be adjusted with channel (see Table 40)
#define FS_CTRL 0x2B
#define FS_PLLTUNE_SUB 0x0B
#define LEN_FS_PLLTUNE 1

#include <stdio.h>
#include <stdlib.h>
#include <string.h>
Expand Down Expand Up @@ -148,6 +191,7 @@ class DW1000 {
DW1000(int ss, int rst);
~DW1000();
void initialize();
void tune();

// device id, address, etc.
char* getPrintableDeviceIdentifier();
Expand Down Expand Up @@ -189,6 +233,7 @@ class DW1000 {
// SYS_MASK, interrupt handling
void interruptOnSent(boolean val);
void interruptOnReceived(boolean val);
void interruptOnAutomaticAcknowledgeTrigger(boolean val);
void clearInterrupts();

void clearReceiveStatus();
Expand Down

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