RISC-V EDK2 CI report for ALL architectures. #197
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BZ: 2562 https://bugzilla.tianocore.org/show_bug.cgi?id=2562 This pull request is just for reviewing RISC-V CI report logs. This report is CI runs on IA32, X64, ARM, AARCH64 and RISCV64. Signed-off-by: Abner Chang <abner.chang@hpe.com> Cc: Bret Barkelew <Bret.Barkelew@microsoft.com> Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Bob Feng <bob.c.feng@intel.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Zhichao Gao <zhichao.gao@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Chao Zhang <chao.b.zhang@intel.com> Cc: Xiaoyu Lu <xiaoyux.lu@intel.com> Cc: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Siyuan Fu <siyuan.fu@intel.com> Cc: Gilbert Chen <gilbert.chen@hpe.com> Cc: Daniel Helmut Schaefer <daniel.schaefer@hpe.com>
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BZ: 2562
https://bugzilla.tianocore.org/show_bug.cgi?id=2562
This report was run on all architectures (IA32, X64, ARM, AARCH64, RISCV64)
This pull request is just for reviewing RISC-V CI report logs. Let component owners know RISC-V port on EDK2 passed CI test.
Signed-off-by: Abner Chang abner.chang@hpe.com