build(deps): bump actions/checkout from 3 to 4

.github/workflows/build.yml

@@ -67,13 +67,13 @@ jobs:
             # Determine the repo and leave that unset to use the normal checkout behavior
             # of using the merge commit instead of HEAD
             case $GITHUB_REPOSITORY in
-              "apache/nuttx")
+              "tiiuae/nuttx")
                 # OS
                 echo "Triggered by change in OS"
                 APPS_REF=$REF_NAME
                 ;;
 
-              "apache/nuttx-apps" )
+              "tiiuae/incubator-nuttx-apps" )
                 # APPS
                 OS_REF=$REF_NAME
                 echo "Triggered by change in APPS"
@@ -89,19 +89,19 @@ jobs:
           echo "app_ref=$APPS_REF" >> $GITHUB_OUTPUT
 
       - name: Checkout nuttx repo
-        uses: actions/checkout@v3
+        uses: actions/checkout@v4
         with:
-          repository: apache/nuttx
+          repository: tiiuae/nuttx
           ref: ${{ steps.gittargets.outputs.os_ref }}
           path: sources/nuttx
           fetch-depth: 1
       - name: Checkout nuttx repo tags
         run: git -C sources/nuttx fetch --tags
 
       - name: Checkout apps repo
-        uses: actions/checkout@v3
+        uses: actions/checkout@v4
         with:
-          repository: apache/nuttx-apps
+          repository: tiiuae/incubator-nuttx-apps
           ref: ${{ steps.gittargets.outputs.apps_ref }}
           path: sources/apps
           fetch-depth: 1
@@ -123,7 +123,7 @@ jobs:
 
     strategy:
       matrix:
-        boards: [arm-01, arm-02, arm-03, arm-04, arm-05, arm-06, arm-07, arm-08, arm-09, arm-10, arm-11, arm-12, arm-13, other, risc-v, sim-01, sim-02, xtensa, codechecker]
+        boards: [arm-12, risc-v]
 
     steps:
       - name: Download Source Artifact
@@ -173,6 +173,7 @@ jobs:
         continue-on-error: true
 
   macOS:
+    if: ${{ false }}  # disable for now
     permissions:
       contents: none
     runs-on: macos-13

.github/workflows/check.yml

@@ -30,9 +30,9 @@ jobs:
 
     steps:
       - name: Checkout nuttx repo
-        uses: actions/checkout@v3
+        uses: actions/checkout@v4
         with:
-          repository: apache/nuttx
+          repository: tiiuae/nuttx
           path: nuttx
           fetch-depth: 0
 

.github/workflows/doc.yml

@@ -27,7 +27,7 @@ jobs:
   build-html:
     runs-on: ubuntu-latest
     steps:
-      - uses: actions/checkout@v3
+      - uses: actions/checkout@v4
       - uses: actions/setup-python@v4
         with:
           python-version: '3.8'

.github/workflows/docker_linux.yml

@@ -46,7 +46,7 @@ jobs:
       IMAGE_TAG: ghcr.io/${{ github.repository }}/apache-nuttx-ci-linux
     steps:
       - name: Checkout repository
-        uses: actions/checkout@v3
+        uses: actions/checkout@v4
 
       - name: Set up Docker Buildx
         uses: docker/setup-buildx-action@v2

.github/workflows/lint.yml

@@ -17,7 +17,7 @@ jobs:
     name: Lint
     runs-on: ubuntu-latest
     steps:
-      - uses: actions/checkout@v3
+      - uses: actions/checkout@v4
         with:
           fetch-depth: 0
       - run: mkdir super-linter.report

arch/arm/src/stm32f7/stm32_ethernet.c

@@ -3136,7 +3136,9 @@ static inline int stm32_dm9161(struct stm32_ethmac_s *priv)
 
 static int stm32_phyinit(struct stm32_ethmac_s *priv)
 {
+#ifdef CONFIG_STM32F7_AUTONEG
   volatile uint32_t timeout;
+#endif
   uint32_t regval;
   uint16_t phyval;
   int ret;

arch/risc-v/src/litex/litex_sdio.c

@@ -860,12 +860,10 @@ static int litex_recvsetup(struct sdio_dev_s *dev, uint8_t *buffer,
 
   /* flush CPU d-cache */
 
-#ifndef CONFIG_LITEX_COHERENT_DMA
   up_invalidate_dcache_all();
-#endif
 
   putreg32(0, LITEX_SDBLOCK2MEM_DMA_ENABLE);
-  putreg32((uintptr_t)(&buffer[4]), LITEX_SDBLOCK2MEM_DMA_BASE);
+  putreg32((uintptr_t)buffer >> 32, LITEX_SDBLOCK2MEM_DMA_BASE);
   putreg32((uintptr_t)buffer, LITEX_SDBLOCK2MEM_DMA_BASE + 0x04);
   putreg32(nbytes, LITEX_SDBLOCK2MEM_DMA_LENGTH);
   putreg32(1, LITEX_SDBLOCK2MEM_DMA_ENABLE);
@@ -905,12 +903,10 @@ static int litex_sendsetup(struct sdio_dev_s *dev,
 
   /* flush CPU d-cache */
 
-#ifndef CONFIG_LITEX_COHERENT_DMA
   up_invalidate_dcache_all();
-#endif
 
   putreg32(0, LITEX_SDMEM2BLOCK_DMA_ENABLE);
-  putreg32((uintptr_t)(&buffer[4]), LITEX_SDMEM2BLOCK_DMA_BASE);
+  putreg32((uintptr_t)buffer >> 32, LITEX_SDMEM2BLOCK_DMA_BASE);
   putreg32((uintptr_t)buffer, LITEX_SDMEM2BLOCK_DMA_BASE + 0x04);
   putreg32(nbytes, LITEX_SDMEM2BLOCK_DMA_LENGTH);
   putreg32(1, LITEX_SDMEM2BLOCK_DMA_ENABLE);

arch/risc-v/src/mpfs/.gitignore

@@ -0,0 +1 @@
+/crypto

arch/risc-v/src/mpfs/Kconfig

@@ -243,15 +243,48 @@ config MPFS_HAVE_UART4
 	select UART4_SERIALDRIVER
 	select ARCH_HAVE_SERIAL_TERMIOS
 
+config MPFS_HAVE_UART5
+	bool
+	depends on MPFS_FPGA_UART
+	default n
+	select UART5_SERIALDRIVER
+	select ARCH_HAVE_SERIAL_TERMIOS
+
+config MPFS_HAVE_UART6
+	bool
+	depends on MPFS_FPGA_UART
+	default n
+	select UART6_SERIALDRIVER
+	select ARCH_HAVE_SERIAL_TERMIOS
+
+config MPFS_HAVE_UART7
+	bool
+	depends on MPFS_FPGA_UART
+	default n
+	select UART7_SERIALDRIVER
+	select ARCH_HAVE_SERIAL_TERMIOS
+
 # These are the peripheral selections proper
 
+config MPFS_SPI
+	bool
+	default n
+
 config MPFS_SPI0
 	bool "SPI 0"
 	default n
+	select MPFS_SPI
 
 config MPFS_SPI1
 	bool "SPI 1"
 	default n
+	select MPFS_SPI
+
+config MPFS_FPGA_UART
+	bool "FPGA uarts"
+	default n
+	---help---
+		Use FPGA UARTs instead of MSS UARTS.
 
 config MPFS_UART0
 	bool "UART 0"
@@ -288,6 +321,30 @@ config MPFS_UART4
 	select ARCH_HAVE_SERIAL_TERMIOS
 	select MPFS_HAVE_UART4
 
+config MPFS_UART5
+	bool "UART 5"
+	depends on MPFS_FPGA_UART
+	default n
+	select ARCH_HAVE_UART5
+	select ARCH_HAVE_SERIAL_TERMIOS
+	select MPFS_HAVE_UART5
+
+config MPFS_UART6
+	bool "UART 6"
+	depends on MPFS_FPGA_UART
+	default n
+	select ARCH_HAVE_UART6
+	select ARCH_HAVE_SERIAL_TERMIOS
+	select MPFS_HAVE_UART6
+
+config MPFS_UART7
+	bool "UART 7"
+	depends on MPFS_FPGA_UART
+	default n
+	select ARCH_HAVE_UART7
+	select ARCH_HAVE_SERIAL_TERMIOS
+	select MPFS_HAVE_UART7
+
 config MPFS_I2C0
 	bool "I2C 0"
 	select ARCH_HAVE_I2CRESET
@@ -398,7 +455,7 @@ config MPFS_IHC_LINUX_ON_HART3
 config MPFS_IHC_LINUX_ON_HART4
 	int "Linux on hart4"
 	depends on MPFS_IHC_CLIENT || MPFS_IHC_SBI
-	default 1
+	default 0
 	range 0 1
 	---help---
 		Set this to 1 if U-boot / Linux is running on hart4
@@ -451,6 +508,43 @@ config MPFS_IHC_RPMSG_CH2
 		Use this only if using 2 x RPMSG channels.  This makes the NuttX work as the
 		RPMSG channel 2 client.
 
+config MPFS_IHC_WITH_HSS
+	bool "IHC with HSS"
+	depends on MPFS_IHC_CLIENT
+	default n
+	---help---
+		Set this to true if using IHC with HSS bootloader
+
+config MPFS_CH1_VRING_SHMEM_ADDR
+	hex "Channel 1 Vring shared memory start"
+	default 0xA2410000
+	depends on MPFS_IHC_CLIENT
+
+config MPFS_CH1_VRING0_DESC_ADDR
+	hex "Channel 1 Vring0 descriptor area"
+	default 0xA2400000
+	depends on MPFS_IHC_CLIENT
+
+config MPFS_CH1_VRING1_DESC_ADDR
+	hex "Channel 1 Vring1 descriptor area"
+	default 0xA2408000
+	depends on MPFS_IHC_CLIENT
+
+config MPFS_CH2_VRING_SHMEM_ADDR
+	hex "Channel 2 Vring shared memory start"
+	default 0xA2460000
+	depends on MPFS_IHC_CLIENT && MPFS_IHC_RPMSG_CH2
+
+config MPFS_CH2_VRING0_DESC_ADDR
+	hex "Channel 2 Vring0 descriptor area"
+	default 0xA2450000
+	depends on MPFS_IHC_CLIENT && MPFS_IHC_RPMSG_CH2
+
+config MPFS_CH2_VRING1_DESC_ADDR
+	hex "Channel 2 Vring1 descriptor area"
+	default 0xA2458000
+	depends on MPFS_IHC_CLIENT && MPFS_IHC_RPMSG_CH2
+
 config MPFS_ETHMAC
 	bool
 	default n
@@ -528,12 +622,6 @@ config MPFS_COREPWM0_BASE
 	default 0x44000000
 	depends on MPFS_COREPWM0
 
-config MPFS_COREPWM0_PWMCLK
-	int "Clock frequency of the CorePWM0 block (Hz)"
-	default 25000000
-	range 1000000 100000000
-	depends on MPFS_COREPWM0
-
 config MPFS_COREPWM0_REGWIDTH
 	int "Width of the PWM register (8, 16 or 32 bits)"
 	default 32
@@ -557,12 +645,6 @@ config MPFS_COREPWM1_BASE
 	default 0x45000000
 	depends on MPFS_COREPWM1
 
-config MPFS_COREPWM1_PWMCLK
-	int "Clock frequency of the CorePWM1 block (Hz)"
-	default 25000000
-	range 1000000 100000000
-	depends on MPFS_COREPWM1
-
 config MPFS_COREPWM1_REGWIDTH
 	int "Width of the PWM register (8, 16 or 32 bits)"
 	default 32
@@ -575,6 +657,56 @@ config MPFS_COREPWM1_NCHANNELS
 	range 1 16
 	depends on MPFS_COREPWM1
 
+comment "CAN-FD Options"
+
+config MPFS_HAVE_CANFD
+	bool "CAN FD"
+	select ARCH_HAVE_CAN_ERRORS
+	select NET_CAN_HAVE_CANFD
+	select NET_CAN_EXTID
+	select NET_CAN_HAVE_TX_DEADLINE
+	default n
+
+config MPFS_CANFD0
+	bool "MPFS FPGA CANFD0 IP block configured"
+	default n
+	depends on MPFS_HAVE_CANFD
+
+config MPFS_CANFD_BASE0
+	hex "Base address for the CANFD0 instance"
+	default 0x46000000
+	depends on MPFS_CANFD0
+
+config MPFS_CANFD_ARBI_BITRATE0
+	int "CANFD0 Arbitration phase bitrate"
+	default 1000000
+	depends on MPFS_CANFD0
+
+config MPFS_CANFD_DATA_BITRATE0
+	int "CANFD0 Data phase bitrate"
+	default 4000000
+	depends on MPFS_CANFD0
+
+config MPFS_CANFD1
+	bool "MPFS FPGA CANFD1 IP block configured"
+	default n
+	depends on MPFS_HAVE_CANFD
+
+config MPFS_CANFD_BASE1
+	hex "Base address for the CANFD1 instance"
+	default 0x47000000
+	depends on MPFS_CANFD1
+
+config MPFS_CANFD_ARBI_BITRATE1
+	int "CANFD1 Arbitration phase bitrate"
+	default 1000000
+	depends on MPFS_CANFD1
+
+config MPFS_CANFD_DATA_BITRATE1
+	int "CANFD1 Data phase bitrate"
+	default 4000000
+	depends on MPFS_CANFD1
+
 endmenu
 
 config MPFS_DMA
@@ -740,3 +872,13 @@ config ARCH_MPU_HAS_NO4
 
 config ARCH_MPU_HAS_NAPOT
 	default y
+
+config MPFS_CRYPTO
+	bool "Enable MPFS HW crypto"
+	default n
+
+if MPFS_CRYPTO
+config MPFS_CRYPTO_DMA
+	bool "Enable MPFS HW crypto DMA"
+	default y
+endif