Make it clear that the address randomization is not ASLR

hugo/content/hw/_index.md

@@ -65,25 +65,31 @@ the FPGA bitstream.
 The RAM is 128 kiB. The firmware clears the RAM before loading a the
 TKey device app into RAM.
 
-# Address Space Layout Randomization (ASLR)
+## Address Randomization
 
-The TKey hardware includes a simple form of RAM memory protection. The
-memory protection is based on two separate mechanisms:
+The TKey hardware includes a simple form of RAM memory protection from
+external threats. This might mitigate some of the problems of a warm
+boot attack potentially reading out all the RAM contents.
 
-1. Address Space Layout Randomisation (ASLR)
+The memory protection is based on two separate mechanisms:
+
+1. Address randomisation
 2. Address dependent data scrambling
 
-The ASLR is implemented by XORing the CPU address with the contents of
-the `ADDR_RAM_ASLR` register in the TK1 core. The result is used as
-the RAM address. The ASLR is set up by the firmware as part of loading
-the TKey device app. The ASLR will be transparent to the app, and
-developers does not have to do anything to use it.
+The address randomisation is implemented by XORing the CPU address
+with the contents of the `ADDR_RAM_ASLR` register in the TK1 core. The
+result is used as the RAM address. This is set up by the firmware as
+part of loading the TKey device app. The addresses will be transparent
+to the device app and developers don't have to do anything to use it.
 
-For more information about the ASLR, please see the Tillitis Key
-[system
+For more information about this, please see the Tillitis Key [system
 description](https://github.com/tillitis/tillitis-key1/blob/main/doc/system_description/system_description.md)
 (in the tillitis-key1 repository).
 
+Note that this, despite the name of the register, is not layout
+randomization. The running app doesn't have offsets to, say, library
+functions randomized.
+
 ## RAM Scrambler
 
 The data scrambling is implemented by XORing the data written to the
@@ -94,8 +100,8 @@ The same pair or XOR operations is also performed on the data read out
 from the RAM.
 
 The data scrambling is set up by the firmware as part of loading the
-TKey device app. The scrambling will be transparent to the app, and
-developers does not have to do anything to use it.
+TKey device app. The scrambling will be transparent to the app and
+developers don't have to do anything to use it.
 
 
 ## Timer

hugo/content/intro/_index.md

@@ -26,7 +26,7 @@ TKey specifications:
 
 - 32-bit RISC-V CPU running at 18 MHz
 - Execution monitor
-- Hardware-assisted ASLR and RAM scrambling
+- Hardware-assisted address randomization and RAM scrambling
 - 128 kiB RAM for TKey device applications
 - 2 kiB firmware RAM
 - 6 kiB ROM

hugo/content/memory/_index.md

@@ -94,7 +94,7 @@ write access.
 | `BLAKE2S`         | r/w   | r         | 4B     | u32      |           | Function pointer to a BLAKE2S function in the firmware.                 |
 | `CDI_FIRST`       | r/w   | r         | 32B    | u8[32]   |           | The computed Compound Device Identifier (CDI).                          |
 | `CDI_LAST`        |       | r         |        |          |           | Last word of CDI.                                                       |
-| `RAM_ASLR`        | w     | invisible | 4B     | u32      |           | Address Space Randomization seed value for the RAM.                     |
+| `RAM_ASLR`        | w     | invisible | 4B     | u32      |           | Seed value for the RAM randomization.                                   |
 | `RAM_SCRAMBLE`    | w     | invisible | 4B     | u32      |           | Data scrambling seed value for the RAM.                                 |
 | `CPU_MON_CTRL`    | w     | w         | 4B     | u32      |           | Bit 0 enables CPU execution monitor. Can't be unset. Lock addresses.    |
 | `CPU_MON_FIRST`   | w     | w         | 4B     | u32      |           | First address of the area monitored for execution attempts.             |