Make initial public release

tillitis · Sep 19, 2022 · dcd8319 · dcd8319
1 parent 814a050
commit dcd8319
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Showing 12 changed files with 684 additions and 0 deletions.
diff --git a/.gitignore b/.gitignore
@@ -15,3 +15,4 @@ GTAGS
 *.depend_raw
 *.swp
 *.patch
+.cache
diff --git a/Makefile b/Makefile
@@ -337,3 +337,8 @@ endif
 
 print-%:
 	@echo '$*=$($*)'
+
+
+.PHONY: update-mem-include
+update-mem-include:
+	cp -af ../tillitis-key1/hw/application_fpga/fw/mta1_mkdf_mem.h include/hw/riscv/mta1_mkdf_mem.h
diff --git a/configs/devices/riscv32-softmmu/default.mak b/configs/devices/riscv32-softmmu/default.mak
@@ -13,3 +13,4 @@ CONFIG_SIFIVE_E=y
 CONFIG_SIFIVE_U=y
 CONFIG_RISCV_VIRT=y
 CONFIG_OPENTITAN=y
+CONFIG_MTA1_MKDF=y
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
@@ -17,6 +17,10 @@ config MICROCHIP_PFSOC
     select SIFIVE_PLIC
     select UNIMP
 
+config MTA1_MKDF
+    bool
+    select UNIMP
+
 config OPENTITAN
     bool
     select IBEX

diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
@@ -2,6 +2,7 @@ riscv_ss = ss.source_set()
 riscv_ss.add(files('boot.c'), fdt)
 riscv_ss.add(when: 'CONFIG_RISCV_NUMA', if_true: files('numa.c'))
 riscv_ss.add(files('riscv_hart.c'))
+riscv_ss.add(when: 'CONFIG_MTA1_MKDF', if_true: files('mta1_mkdf.c'))
 riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
 riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
 riscv_ss.add(when: 'CONFIG_SHAKTI_C', if_true: files('shakti_c.c'))