You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
It is quite possible that we could raise the clock frequency of the FPGA design. In order to do so we should analyze the timing after P&R and see what can be done. And then try to modify the design to improve the clock frequency.
The text was updated successfully, but these errors were encountered:
It is quite possible that we could raise the clock frequency of the FPGA design. In order to do so we should analyze the timing after P&R and see what can be done. And then try to modify the design to improve the clock frequency.
The text was updated successfully, but these errors were encountered: