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Merge branch 'clock-crossing' into tomu
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@osresearch
osresearch committed Jan 18, 2019
2 parents e2257c8 + 84959e7 commit 22f8d62
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45 changes: 45 additions & 0 deletions .travis.yml
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language: python

jobs:
include:
- stage: test
python: 2.7
env: TOXENV=py27
name: "Python 2.7"
- python: 3.4
env: TOXENV=py34
name: "Python 3.4"
- python: 3.5
env: TOXENV=py35
name: "Python 3.5"
- python: 3.6
env: TOXENV=py36
name: "Python 3.6"
- stage: deploy
python: 3.6
name: "Upload dev version to PyPi"
script: ./.push-to-pypi.sh

stages:
- test
- name: deploy
if: branch = master

install:
- git fetch --tags
- cd programmer
- pip install --upgrade pip
- pip install --upgrade tox
- pip install --upgrade setuptools
- pip install --upgrade setuptools_scm
- pip install --upgrade wheel
- pip install --upgrade twine

script:
- tox

notifications:
email: false

git:
depth: false
14 changes: 12 additions & 2 deletions boards/TinyFPGA_BX/Makefile
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Expand Up @@ -22,12 +22,22 @@ PKG = cm81

all: $(PROJ).rpt fw.bin

%.json: %.v ../../common/*.v
yosys -q -p 'synth_ice40 -top $(PROJ) -json $@' $^
%.blif: %.v ../../common/*.v
yosys -p 'synth_ice40 -top $(PROJ) -blif $@' $^
yosys -q -p 'synth_ice40 -top $(PROJ) -blif $@' $^

%.asc: $(PIN_DEF) %.blif
NO-%.asc: $(PIN_DEF) %.blif
arachne-pnr -d 8k -P $(PKG) -o $@ -p $^

%.asc: $(PIN_DEF) %.json
nextpnr-ice40 \
--$(DEVICE) \
--package $(PKG) \
--asc $@ \
--pcf $(PIN_DEF) \
--json $(basename $@).json \

%.bin: %.asc
icepack $< $@

Expand Down
50 changes: 43 additions & 7 deletions boards/TinyFPGA_BX/bootloader.v
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Expand Up @@ -20,6 +20,8 @@ module bootloader (
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
wire clk_48mhz;
wire lock;
wire reset = !lock;

SB_PLL40_CORE #(
.DIVR(4'b0000),
Expand All @@ -43,13 +45,18 @@ module bootloader (
.RESETB(1'b1),
.BYPASS(1'b0),
.LATCHINPUTVALUE(),
.LOCK(),
.LOCK(lock),
.SDI(),
.SDO(),
.SCLK()
);

reg clk_24mhz;
reg clk_12mhz;
always @(posedge clk_48mhz) clk_24mhz = !clk_24mhz;
always @(posedge clk_24mhz) clk_12mhz = !clk_12mhz;

wire clk = clk_12mhz; // quarter speed clock

////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
Expand All @@ -74,7 +81,6 @@ module bootloader (
////////
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
wire reset;
wire usb_p_tx;
wire usb_n_tx;
wire usb_p_rx;
Expand All @@ -83,6 +89,7 @@ module bootloader (

tinyfpga_bootloader tinyfpga_bootloader_inst (
.clk_48mhz(clk_48mhz),
.clk(clk),
.reset(reset),
.usb_p_tx(usb_p_tx),
.usb_n_tx(usb_n_tx),
Expand All @@ -98,10 +105,39 @@ module bootloader (
);

assign pin_pu = 1'b1;
assign pin_usbp = usb_tx_en ? usb_p_tx : 1'bz;
assign pin_usbn = usb_tx_en ? usb_n_tx : 1'bz;
assign usb_p_rx = usb_tx_en ? 1'b1 : pin_usbp;
assign usb_n_rx = usb_tx_en ? 1'b0 : pin_usbn;

assign reset = 1'b0;
wire usb_p_rx_io;
wire usb_n_rx_io;
assign usb_p_rx = usb_tx_en ? 1'b1 : usb_p_rx_io;
assign usb_n_rx = usb_tx_en ? 1'b0 : usb_n_rx_io;

tristate usbn_buffer(
.pin(pin_usbn),
.enable(usb_tx_en),
.data_in(usb_n_rx_io),
.data_out(usb_n_tx)
);

tristate usbp_buffer(
.pin(pin_usbp),
.enable(usb_tx_en),
.data_in(usb_p_rx_io),
.data_out(usb_p_tx)
);
endmodule

module tristate(
inout pin,
input enable,
input data_out,
output data_in
);
SB_IO #(
.PIN_TYPE(6'b1010_01) // tristatable output
) buffer(
.PACKAGE_PIN(pin),
.OUTPUT_ENABLE(enable),
.D_IN_0(data_in),
.D_OUT_0(data_out)
);
endmodule
84 changes: 42 additions & 42 deletions boards/TinyFPGA_BX/pins.pcf
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Expand Up @@ -3,46 +3,46 @@
# Package: CM81
###############################################################################

#set_io pin_1 A2
#set_io pin_2 A1
#set_io pin_3 B1
#set_io pin_4 C2
#set_io pin_5 C1
#set_io pin_6 D2
#set_io pin_7 D1
#set_io pin_8 E2
#set_io pin_9 E1
#set_io pin_10 G2
#set_io pin_11 H1
#set_io pin_12 J1
#set_io pin_13 H2
#set_io pin_14 H9
#set_io pin_15 D9
#set_io pin_16 D8
#set_io pin_17 C9
#set_io pin_18 A9
#set_io pin_19 B8
#set_io pin_20 A8
#set_io pin_21 B7
#set_io pin_22 A7
#set_io pin_23 B6
#set_io pin_24 A6
#set_io pin_25 G1
#set_io pin_26 J3
#set_io pin_27 J4
#set_io pin_28 H4
set_io pin_29_miso H7
set_io pin_30_cs F7
set_io pin_31_mosi G6
set_io pin_32_sck G7
#set_io pin_33 J8
#set_io pin_34 G9
#set_io pin_35 J9
#set_io pin_36 E8
#set_io pin_37 J2
set_io pin_led B3
set_io pin_usbp B4
set_io pin_usbn A4
set_io pin_pu A3
set_io pin_clk B2
set_io -nowarn pin_1 A2
set_io -nowarn pin_2 A1
set_io -nowarn pin_3 B1
set_io -nowarn pin_4 C2
set_io -nowarn pin_5 C1
set_io -nowarn pin_6 D2
set_io -nowarn pin_7 D1
set_io -nowarn pin_8 E2
set_io -nowarn pin_9 E1
set_io -nowarn pin_10 G2
set_io -nowarn pin_11 H1
set_io -nowarn pin_12 J1
set_io -nowarn pin_13 H2
set_io -nowarn pin_14 H9
set_io -nowarn pin_15 D9
set_io -nowarn pin_16 D8
set_io -nowarn pin_17 C9
set_io -nowarn pin_18 A9
set_io -nowarn pin_19 B8
set_io -nowarn pin_20 A8
set_io -nowarn pin_21 B7
set_io -nowarn pin_22 A7
set_io -nowarn pin_23 B6
set_io -nowarn pin_24 A6
set_io -nowarn pin_25 G1
set_io -nowarn pin_26 J3
set_io -nowarn pin_27 J4
set_io -nowarn pin_28 H4
set_io -nowarn pin_29_miso H7
set_io -nowarn pin_30_cs F7
set_io -nowarn pin_31_mosi G6
set_io -nowarn pin_32_sck G7
set_io -nowarn pin_33 J8
set_io -nowarn pin_34 G9
set_io -nowarn pin_35 J9
set_io -nowarn pin_36 E8
set_io -nowarn pin_37 J2
set_io -nowarn pin_led B3
set_io -nowarn pin_usbp B4
set_io -nowarn pin_usbn A4
set_io -nowarn pin_pu A3
set_io -nowarn pin_clk B2

53 changes: 53 additions & 0 deletions common/strobe.v
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@@ -0,0 +1,53 @@
module strobe(
input clk_in,
input clk_out,
input strobe_in,
output strobe_out,
input [WIDTH-1:0] data_in,
output [WIDTH-1:0] data_out
);
parameter WIDTH = 1;
parameter DELAY = 2; // 2 for metastability, larger for testing

`define CLOCK_CROSS
`ifdef CLOCK_CROSS
reg flag;
reg prev_strobe;
reg [DELAY:0] sync;
reg [WIDTH-1:0] data;

// flip the flag and clock in the data when strobe is high
always @(posedge clk_in) begin
//if ((strobe_in && !prev_strobe)
//|| (!strobe_in && prev_strobe))
flag <= flag ^ strobe_in;

if (strobe_in)
data <= data_in;

prev_strobe <= strobe_in;
end

// shift through a chain of flipflop to ensure stability
always @(posedge clk_out)
sync <= { sync[DELAY-1:0], flag };

assign strobe_out = sync[DELAY] ^ sync[DELAY-1];
assign data_out = data;
`else
assign strobe_out = strobe_in;
assign data_out = data_in;
`endif
endmodule


module dflip(
input clk,
input in,
output out
);
reg [2:0] d;
always @(posedge clk)
d <= { d[1:0], in };
assign out = d[2];
endmodule
20 changes: 11 additions & 9 deletions common/tinyfpga_bootloader.v
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Original file line number Diff line number Diff line change
@@ -1,5 +1,6 @@
module tinyfpga_bootloader (
input clk_48mhz,
input clk,
input reset,

// USB lines. Split into input vs. output and oe control signal to maintain
Expand All @@ -26,6 +27,7 @@ module tinyfpga_bootloader (
// function.
output boot
);

////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
////////
Expand All @@ -38,7 +40,7 @@ module tinyfpga_bootloader (

reg [5:0] ns_cnt = 0;
wire ns_rst = (ns_cnt == 48);
always @(posedge clk_48mhz) begin
always @(posedge clk) begin
if (ns_rst) begin
ns_cnt <= 0;
end else begin
Expand All @@ -48,7 +50,7 @@ module tinyfpga_bootloader (

reg [9:0] us_cnt = 0;
wire us_rst = (us_cnt == 1000);
always @(posedge clk_48mhz) begin
always @(posedge clk) begin
if (us_rst) begin
us_cnt <= 0;
end else if (ns_rst) begin
Expand All @@ -57,7 +59,7 @@ module tinyfpga_bootloader (
end

reg count_down = 0;
always @(posedge clk_48mhz) begin
always @(posedge clk) begin
if (us_rst) begin
if (count_down) begin
if (led_pwm == 0) begin
Expand All @@ -74,11 +76,10 @@ module tinyfpga_bootloader (
end
end
end
always @(posedge clk_48mhz) pwm_cnt <= pwm_cnt + 1'b1;
always @(posedge clk) pwm_cnt <= pwm_cnt + 1'b1;
assign led = led_pwm > pwm_cnt;



////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
////////
Expand Down Expand Up @@ -136,7 +137,7 @@ module tinyfpga_bootloader (
assign boot = host_presence_timeout || boot_to_user_design;

usb_serial_ctrl_ep ctrl_ep_inst (
.clk(clk_48mhz),
.clk(clk),
.reset(reset),
.dev_addr(dev_addr),

Expand All @@ -163,7 +164,7 @@ module tinyfpga_bootloader (
);

usb_spi_bridge_ep usb_spi_bridge_ep_inst (
.clk(clk_48mhz),
.clk(clk),
.reset(reset),

// out endpoint interface
Expand Down Expand Up @@ -204,7 +205,8 @@ module tinyfpga_bootloader (
.NUM_OUT_EPS(5'd2),
.NUM_IN_EPS(5'd3)
) usb_fs_pe_inst (
.clk(clk_48mhz),
.clk_48mhz(clk_48mhz),
.clk(clk),
.reset(reset),

.usb_p_tx(usb_p_tx),
Expand Down Expand Up @@ -246,7 +248,7 @@ module tinyfpga_bootloader (
// host presence detection
////////////////////////////////////////////////////////////////////////////////

always @(posedge clk_48mhz) begin
always @(posedge clk) begin
if (sof_valid) begin
host_presence_timer <= 0;
host_presence_timeout <= 0;
Expand Down
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