New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Various FPGA fixes for yosys synthesis #21

wants to merge 4 commits into
base: master


None yet
1 participant
Copy link

smunaut commented Sep 2, 2018

See individual commits descriptions for details

smunaut added some commits Sep 2, 2018

boards/TinyFPGA_BX: Don't rely on tristate inference
This doesn't work in recent yosys/{arachnepnr,nextpnr}, so manually
instantiate SB_IO

Signed-off-by: Sylvain Munaut <>
common/serial: Fix syntax error
Signed-off-by: Sylvain Munaut <>
common: Make sure RAM inference works with yosys
icecube doesn't care about init values, but yosys does and you can't
satisfy them with HW RAM module.

So here we remove all the init values and we make sure the reads are
not dependent on the reset line

Signed-off-by: Sylvain Munaut <>
common: Make sure to always assign all 'reg's in processes to avoid l…

If you don't assign all 'reg's in a process, this effectively describes
a latch, and the HW doesn't have any HW latches which leads yosys to create
a logic loop, which is definitely not good in FPGA !

Signed-off-by: Sylvain Munaut <>
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment