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Various FPGA fixes for yosys synthesis #21

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smunaut commented Sep 2, 2018

See individual commits descriptions for details

smunaut added some commits Sep 2, 2018

boards/TinyFPGA_BX: Don't rely on tristate inference
This doesn't work in recent yosys/{arachnepnr,nextpnr}, so manually
instantiate SB_IO

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
common/serial: Fix syntax error
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
common: Make sure RAM inference works with yosys
icecube doesn't care about init values, but yosys does and you can't
satisfy them with HW RAM module.

So here we remove all the init values and we make sure the reads are
not dependent on the reset line

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
common: Make sure to always assign all 'reg's in processes to avoid l…
…atches

If you don't assign all 'reg's in a process, this effectively describes
a latch, and the HW doesn't have any HW latches which leads yosys to create
a logic loop, which is definitely not good in FPGA !

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
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