Various FPGA fixes for yosys synthesis #21
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This doesn't work in recent yosys/{arachnepnr,nextpnr}, so manually
instantiate SB_IO
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
icecube doesn't care about init values, but yosys does and you can't satisfy them with HW RAM module. So here we remove all the init values and we make sure the reads are not dependent on the reset line Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
…atches If you don't assign all 'reg's in a process, this effectively describes a latch, and the HW doesn't have any HW latches which leads yosys to create a logic loop, which is definitely not good in FPGA ! Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
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What is the status of this, @tinyfpga? |
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Do you know if this pull request works with the existing test suite? Has it been tested on actual TinyFPGA BX and B2 hardware? |
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