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Improve Reloop to accept constant index offsets. (verilator#2939)
V3Reloop now can roll up indexed assignments between arrays if there is a constant offset between indices on the left and right hand sides, e.g.: a[0] = b[2]; a[1] = b[3]; ... a[x] = b[x + 2];
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,17 @@ | ||
| shift down 1 | ||
| oarray[63] is 0 | ||
| oarray[62] is 63 | ||
| oarray[61] is 62 | ||
| oarray[32] is 33 | ||
| oarray[ 2] is 3 | ||
| oarray[ 1] is 2 | ||
| oarray[ 0] is 1 | ||
| shift up 2 | ||
| oarray[63] is 61 | ||
| oarray[62] is 60 | ||
| oarray[61] is 59 | ||
| oarray[32] is 30 | ||
| oarray[ 2] is 0 | ||
| oarray[ 1] is 2 | ||
| oarray[ 0] is 1 | ||
| *-* All Finished *-* |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,33 @@ | ||
| #!/usr/bin/env perl | ||
| if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } | ||
| # DESCRIPTION: Verilator: Verilog Test driver/expect definition | ||
| # | ||
| # Copyright 2003 by Wilson Snyder. This program is free software; you | ||
| # can redistribute it and/or modify it under the terms of either the GNU | ||
| # Lesser General Public License Version 3 or the Perl Artistic License | ||
| # Version 2.0. | ||
| # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 | ||
|
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| scenarios(simulator => 1); | ||
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| compile( | ||
| verilator_flags2 => ["-unroll-count 1024", | ||
| $Self->wno_unopthreads_for_few_cores(), | ||
| "--stats"], | ||
| ); | ||
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| execute( | ||
| check_finished => 1, | ||
| expect_filename => $Self->{golden_filename}, | ||
| ); | ||
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| if ($Self->{vlt}) { | ||
| # Note, with vltmt this might be split differently, so only checking vlt | ||
| file_grep($Self->{stats}, qr/Optimizations, Reloop iterations\s+(\d+)/i, | ||
| 125); | ||
| file_grep($Self->{stats}, qr/Optimizations, Reloops\s+(\d+)/i, | ||
| 2); | ||
| } | ||
|
|
||
| ok(1); | ||
| 1; |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,50 @@ | ||
| // DESCRIPTION: Verilator: Verilog Test module | ||
| // | ||
| // This file ONLY is placed under the Creative Commons Public Domain, for | ||
| // any use, without warranty, 2020 by Geza Lore. | ||
| // SPDX-License-Identifier: CC0-1.0 | ||
|
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| `define show(x) $display("oarray[%2d] is %2d", x, oarray[x]) | ||
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| module t (/*AUTOARG*/); | ||
|
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| int iarray [63:0]; | ||
| int oarray [63:0]; | ||
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| initial begin | ||
| for (int i = 0; i < 64 ; i = i + 1) begin | ||
| iarray[i] = i; | ||
| oarray[i] = 0; | ||
| end | ||
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| for (int i = 0; i < 63; i = i + 1) begin | ||
| oarray[i] = iarray[i + 1]; | ||
| end | ||
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| $display("shift down 1"); | ||
| `show(63); | ||
| `show(62); | ||
| `show(61); | ||
| `show(32); | ||
| `show(2); | ||
| `show(1); | ||
| `show(0); | ||
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| for (int i = 63; i >= 2 ; i = i - 1) begin | ||
| oarray[i] = iarray[i - 2]; | ||
| end | ||
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| $display("shift up 2"); | ||
| `show(63); | ||
| `show(62); | ||
| `show(61); | ||
| `show(32); | ||
| `show(2); | ||
| `show(1); | ||
| `show(0); | ||
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| $write("*-* All Finished *-*\n"); | ||
| $finish; | ||
| end | ||
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| endmodule |