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A Fractional Divider with Delta-Sigma Modulator and Dual-Mode Divider for Phase-Locked Loop

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Fractional-N-DIV

A Fractional Divider with Delta-Sigma Modulator and Dual-Mode Divider for Phase-Locked Loop.

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├── delta-sigma            # delta-sigma
│   ├── rtl                # verilog 代码
│   ├── tb                 # testbench
├── dual-div               # 双模分频器
│   ├── rtl
│   ├── tb
├── FractionalN            # top
│   ├── rtl
│   └── tb
├── pic
│   ├── diagram            # 系统框图
│   ├── test_res           # 仿真测试结果
│   └── wave               # 波形图
├── doc
└── README.md

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A Fractional Divider with Delta-Sigma Modulator and Dual-Mode Divider for Phase-Locked Loop

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  • Verilog 100.0%