GitHub - tocisz/verilog-vesa-ca: Generate VESA signal showing cellular automata simulation

Name		Name	Last commit message	Last commit date
Latest commit History 6 Commits
ipcore_dir		ipcore_dir
ca3.v		ca3.v
ca_gen.prj		ca_gen.prj
ca_gen.v		ca_gen.v
ca_gen0.prj		ca_gen0.prj
ca_gen0.v		ca_gen0.v
clk_div.v		clk_div.v
my_ram.prj		my_ram.prj
my_ram.v		my_ram.v
sync_gen_1280x1024.v		sync_gen_1280x1024.v
top.prj		top.prj
top.v		top.v
two_lines.prj		two_lines.prj
two_lines.v		two_lines.v
vesa2.ucf		vesa2.ucf

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Generate VESA signal showing cellular automata simulation

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