arch: rv32i: Support up to 64 PMP regions

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

arch/rv32i/src/csr/mod.rs

@@ -23,8 +23,8 @@ pub struct CSR {
     pub minstret: ReadWriteRiscvCsr<u32, minstret::minstret::Register>,
     pub mcycleh: ReadWriteRiscvCsr<u32, mcycle::mcycleh::Register>,
     pub mcycle: ReadWriteRiscvCsr<u32, mcycle::mcycle::Register>,
-    pub pmpcfg: [ReadWriteRiscvCsr<u32, pmpconfig::pmpcfg::Register>; 4],
-    pub pmpaddr: [ReadWriteRiscvCsr<u32, pmpaddr::pmpaddr::Register>; 16],
+    pub pmpcfg: [ReadWriteRiscvCsr<u32, pmpconfig::pmpcfg::Register>; 16],
+    pub pmpaddr: [ReadWriteRiscvCsr<u32, pmpaddr::pmpaddr::Register>; 64],
     pub mie: ReadWriteRiscvCsr<u32, mie::mie::Register>,
     pub mscratch: ReadWriteRiscvCsr<u32, mscratch::mscratch::Register>,
     pub mepc: ReadWriteRiscvCsr<u32, mepc::mepc::Register>,
@@ -58,6 +58,18 @@ pub const CSR: &CSR = &CSR {
         ReadWriteRiscvCsr::new(riscv_csr::csr::PMPCFG1),
         ReadWriteRiscvCsr::new(riscv_csr::csr::PMPCFG2),
         ReadWriteRiscvCsr::new(riscv_csr::csr::PMPCFG3),
+        ReadWriteRiscvCsr::new(riscv_csr::csr::PMPCFG4),
+        ReadWriteRiscvCsr::new(riscv_csr::csr::PMPCFG5),
+        ReadWriteRiscvCsr::new(riscv_csr::csr::PMPCFG6),
+        ReadWriteRiscvCsr::new(riscv_csr::csr::PMPCFG7),
+        ReadWriteRiscvCsr::new(riscv_csr::csr::PMPCFG8),
+        ReadWriteRiscvCsr::new(riscv_csr::csr::PMPCFG9),
+        ReadWriteRiscvCsr::new(riscv_csr::csr::PMPCFG10),
+        ReadWriteRiscvCsr::new(riscv_csr::csr::PMPCFG11),
+        ReadWriteRiscvCsr::new(riscv_csr::csr::PMPCFG12),
+        ReadWriteRiscvCsr::new(riscv_csr::csr::PMPCFG13),
+        ReadWriteRiscvCsr::new(riscv_csr::csr::PMPCFG14),
+        ReadWriteRiscvCsr::new(riscv_csr::csr::PMPCFG15),
     ],
     pmpaddr: [
         ReadWriteRiscvCsr::new(riscv_csr::csr::PMPADDR0),
@@ -76,6 +88,54 @@ pub const CSR: &CSR = &CSR {
         ReadWriteRiscvCsr::new(riscv_csr::csr::PMPADDR13),
         ReadWriteRiscvCsr::new(riscv_csr::csr::PMPADDR14),
         ReadWriteRiscvCsr::new(riscv_csr::csr::PMPADDR15),
+        ReadWriteRiscvCsr::new(riscv_csr::csr::PMPADDR16),
+        ReadWriteRiscvCsr::new(riscv_csr::csr::PMPADDR17),
+        ReadWriteRiscvCsr::new(riscv_csr::csr::PMPADDR18),
+        ReadWriteRiscvCsr::new(riscv_csr::csr::PMPADDR19),
+        ReadWriteRiscvCsr::new(riscv_csr::csr::PMPADDR20),
+        ReadWriteRiscvCsr::new(riscv_csr::csr::PMPADDR21),
+        ReadWriteRiscvCsr::new(riscv_csr::csr::PMPADDR22),
+        ReadWriteRiscvCsr::new(riscv_csr::csr::PMPADDR23),
+        ReadWriteRiscvCsr::new(riscv_csr::csr::PMPADDR24),
+        ReadWriteRiscvCsr::new(riscv_csr::csr::PMPADDR25),
+        ReadWriteRiscvCsr::new(riscv_csr::csr::PMPADDR26),
+        ReadWriteRiscvCsr::new(riscv_csr::csr::PMPADDR27),
+        ReadWriteRiscvCsr::new(riscv_csr::csr::PMPADDR28),
+        ReadWriteRiscvCsr::new(riscv_csr::csr::PMPADDR29),
+        ReadWriteRiscvCsr::new(riscv_csr::csr::PMPADDR30),
+        ReadWriteRiscvCsr::new(riscv_csr::csr::PMPADDR31),
+        ReadWriteRiscvCsr::new(riscv_csr::csr::PMPADDR32),
+        ReadWriteRiscvCsr::new(riscv_csr::csr::PMPADDR33),
+        ReadWriteRiscvCsr::new(riscv_csr::csr::PMPADDR34),
+        ReadWriteRiscvCsr::new(riscv_csr::csr::PMPADDR35),
+        ReadWriteRiscvCsr::new(riscv_csr::csr::PMPADDR36),
+        ReadWriteRiscvCsr::new(riscv_csr::csr::PMPADDR37),
+        ReadWriteRiscvCsr::new(riscv_csr::csr::PMPADDR38),
+        ReadWriteRiscvCsr::new(riscv_csr::csr::PMPADDR39),
+        ReadWriteRiscvCsr::new(riscv_csr::csr::PMPADDR40),
+        ReadWriteRiscvCsr::new(riscv_csr::csr::PMPADDR41),
+        ReadWriteRiscvCsr::new(riscv_csr::csr::PMPADDR42),
+        ReadWriteRiscvCsr::new(riscv_csr::csr::PMPADDR43),
+        ReadWriteRiscvCsr::new(riscv_csr::csr::PMPADDR44),
+        ReadWriteRiscvCsr::new(riscv_csr::csr::PMPADDR45),
+        ReadWriteRiscvCsr::new(riscv_csr::csr::PMPADDR46),
+        ReadWriteRiscvCsr::new(riscv_csr::csr::PMPADDR47),
+        ReadWriteRiscvCsr::new(riscv_csr::csr::PMPADDR48),
+        ReadWriteRiscvCsr::new(riscv_csr::csr::PMPADDR49),
+        ReadWriteRiscvCsr::new(riscv_csr::csr::PMPADDR50),
+        ReadWriteRiscvCsr::new(riscv_csr::csr::PMPADDR51),
+        ReadWriteRiscvCsr::new(riscv_csr::csr::PMPADDR52),
+        ReadWriteRiscvCsr::new(riscv_csr::csr::PMPADDR53),
+        ReadWriteRiscvCsr::new(riscv_csr::csr::PMPADDR54),
+        ReadWriteRiscvCsr::new(riscv_csr::csr::PMPADDR55),
+        ReadWriteRiscvCsr::new(riscv_csr::csr::PMPADDR56),
+        ReadWriteRiscvCsr::new(riscv_csr::csr::PMPADDR57),
+        ReadWriteRiscvCsr::new(riscv_csr::csr::PMPADDR58),
+        ReadWriteRiscvCsr::new(riscv_csr::csr::PMPADDR59),
+        ReadWriteRiscvCsr::new(riscv_csr::csr::PMPADDR60),
+        ReadWriteRiscvCsr::new(riscv_csr::csr::PMPADDR61),
+        ReadWriteRiscvCsr::new(riscv_csr::csr::PMPADDR62),
+        ReadWriteRiscvCsr::new(riscv_csr::csr::PMPADDR63),
     ],
 };
 

arch/rv32i/src/pmp.rs

@@ -117,7 +117,7 @@ impl PMPRegion {
 
 /// Struct storing region configuration for RISCV PMP.
 pub struct PMPConfig {
-    regions: [Option<PMPRegion>; 8],
+    regions: [Option<PMPRegion>; 32],
     total_regions: usize,
     /// Indicates if the configuration has changed since the last time it was written to hardware.
     is_dirty: Cell<bool>,
@@ -132,7 +132,7 @@ impl Default for PMPConfig {
     /// number of regions on the arty chip
     fn default() -> PMPConfig {
         PMPConfig {
-            regions: [None; 8],
+            regions: [None; 32],
             total_regions: 8,
             is_dirty: Cell::new(true),
             last_configured_for: MapCell::empty(),
@@ -162,7 +162,7 @@ impl PMPConfig {
             panic!("Tock requires at least 4 PMP regions");
         }
         PMPConfig {
-            regions: [None; 8],
+            regions: [None; 32],
             // As we use the PMP TOR setup we only support half the number
             // of regions as hardware supports
             total_regions: pmp_regions / 2,
@@ -194,7 +194,7 @@ impl kernel::mpu::MPU for PMPConfig {
 
     fn disable_mpu(&self) {
         for x in 0..self.total_regions {
-            // If PMP is supported by the core then all 16 register sets must exist
+            // If PMP is supported by the core then all 64 register sets must exist
             // They don't all have to do anything, but let's zero them all just in case.
             match x % 4 {
                 0 => {