refactor: s/regs/registers

Following a brief IRC discussion, update `regs` to `registers`
https://bot.tockos.org/tockbot/tock/2018-07-09/?msg=111467&page=1

arch/cortex-m/src/systick.rs

@@ -1,7 +1,7 @@
 //! ARM Cortex-M SysTick peripheral.
 
 use kernel;
-use kernel::common::regs::{ReadOnly, ReadWrite};
+use kernel::common::registers::{ReadOnly, ReadWrite};
 use kernel::common::StaticRef;
 
 #[repr(C)]

arch/cortex-m0/src/lib.rs

@@ -113,7 +113,7 @@ EXC_RETURN_PSP:
 #[no_mangle]
 pub unsafe extern "C" fn switch_to_user(
     mut user_stack: *const u8,
-    process_regs: &mut [usize; 8],
+    process_registers: &mut [usize; 8],
 ) -> *mut u8 {
     asm!("
     /* Load non-hardware-stacked registers from Process stack */
@@ -123,7 +123,7 @@ pub unsafe extern "C" fn switch_to_user(
     mov r9,  r5
     mov r8,  r4
     ldmia $2!, {r4-r7}
-    subs $2, 32 /* Restore pointer to process_regs
+    subs $2, 32 /* Restore pointer to process_registers
                 /* ldmia! added a 32-byte offset */
 
     /* Load bottom of stack into Process Stack Pointer */
@@ -132,8 +132,8 @@ pub unsafe extern "C" fn switch_to_user(
     /* SWITCH */
     svc 0xff /* It doesn't matter which SVC number we use here */
 
-    /* Store non-hardware-stacked registers in process_regs */
-    /* $2 still points to process_regs because we are clobbering all */
+    /* Store non-hardware-stacked registers in process_registers */
+    /* $2 still points to process_registers because we are clobbering all */
     /* non-hardware-stacked registers */
     str r4, [$2, #16]
     str r5, [$2, #20]
@@ -154,7 +154,7 @@ pub unsafe extern "C" fn switch_to_user(
 
     "
     : "={r0}"(user_stack)
-    : "{r0}"(user_stack), "{r1}"(process_regs)
+    : "{r0}"(user_stack), "{r1}"(process_registers)
     : "r4","r5","r6","r7","r8","r9","r10","r11");
     user_stack as *mut u8
 }

arch/cortex-m3/src/lib.rs

@@ -141,7 +141,7 @@ pub unsafe extern "C" fn switch_to_user(user_stack: *const u8, process_got: *con
 /// r0 is top of user stack, r1 Process GOT
 pub unsafe extern "C" fn switch_to_user(
     mut user_stack: *const u8,
-    process_regs: &mut [usize; 8],
+    process_registers: &mut [usize; 8],
 ) -> *mut u8 {
     asm!("
     /* Load bottom of stack into Process Stack Pointer */
@@ -155,12 +155,12 @@ pub unsafe extern "C" fn switch_to_user(
     svc 0xff /* It doesn't matter which SVC number we use here */
 
     /* Push non-hardware-stacked registers into Process struct's */
-    /* regs field */
+    /* registers field */
     stmia $2, {r4-r11}
 
     mrs $0, PSP /* PSP into r0 */"
     : "={r0}"(user_stack)
-    : "{r0}"(user_stack), "{r1}"(process_regs)
+    : "{r0}"(user_stack), "{r1}"(process_registers)
     : "r4","r5","r6","r7","r8","r9","r10","r11");
     user_stack as *mut u8
 }

arch/cortex-m4/src/lib.rs

@@ -165,7 +165,7 @@ pub unsafe extern "C" fn switch_to_user(user_stack: *const u8, process_got: *con
 /// r0 is top of user stack, r1 Process GOT
 pub unsafe extern "C" fn switch_to_user(
     mut user_stack: *const u8,
-    process_regs: &mut [usize; 8],
+    process_registers: &mut [usize; 8],
 ) -> *mut u8 {
     asm!("
     /* Load bottom of stack into Process Stack Pointer */
@@ -179,12 +179,12 @@ pub unsafe extern "C" fn switch_to_user(
     svc 0xff /* It doesn't matter which SVC number we use here */
 
     /* Push non-hardware-stacked registers into Process struct's */
-    /* regs field */
+    /* registers field */
     stmia $2, {r4-r11}
 
     mrs $0, PSP /* PSP into r0 */"
     : "={r0}"(user_stack)
-    : "{r0}"(user_stack), "{r1}"(process_regs)
+    : "{r0}"(user_stack), "{r1}"(process_registers)
     : "r4","r5","r6","r7","r8","r9","r10","r11");
     user_stack as *mut u8
 }

arch/cortex-m4/src/mpu.rs

@@ -120,13 +120,13 @@ type Region = kernel::mpu::Region;
 
 impl kernel::mpu::MPU for MPU {
     fn enable_mpu(&self) {
-        let regs = &*self.0;
+        let registers = &*self.0;
 
         // Enable the MPU, disable it during HardFault/NMI handlers, allow
         // privileged code access to all unprotected memory.
-        regs.control.set(0b101);
+        registers.control.set(0b101);
 
-        let mpu_type = regs.mpu_type.get();
+        let mpu_type = registers.mpu_type.get();
         let regions = mpu_type.data_regions.get();
         if regions != 8 {
             panic!(
@@ -137,8 +137,8 @@ impl kernel::mpu::MPU for MPU {
     }
 
     fn disable_mpu(&self) {
-        let regs = &*self.0;
-        regs.control.set(0b0);
+        let registers = &*self.0;
+        registers.control.set(0b0);
     }
 
     fn create_region(
@@ -266,10 +266,12 @@ impl kernel::mpu::MPU for MPU {
     }
 
     fn set_mpu(&self, region: Region) {
-        let regs = &*self.0;
+        let registers = &*self.0;
 
-        regs.region_base_address.set(region.base_address());
+        registers.region_base_address.set(region.base_address());
 
-        regs.region_attributes_and_size.set(region.attributes());
+        registers
+            .region_attributes_and_size
+            .set(region.attributes());
     }
 }

chips/cc26xx/src/gpio.rs

@@ -7,7 +7,7 @@
 use core::cell::Cell;
 use core::ops::{Index, IndexMut};
 use ioc;
-use kernel::common::regs::{ReadWrite, WriteOnly};
+use kernel::common::registers::{ReadWrite, WriteOnly};
 use kernel::common::StaticRef;
 use kernel::hil;
 
@@ -78,8 +78,8 @@ impl hil::gpio::Pin for GPIOPin {
         // Disable input in the io configuration
         ioc::IOCFG[self.pin].enable_output();
         // Enable data output
-        let regs = &*self.registers;
-        regs.doe.set(regs.doe.get() | self.pin_mask);
+        let registers = &*self.registers;
+        registers.doe.set(registers.doe.get() | self.pin_mask);
     }
 
     fn make_input(&self) {
@@ -92,23 +92,23 @@ impl hil::gpio::Pin for GPIOPin {
     }
 
     fn set(&self) {
-        let regs = &*self.registers;
-        regs.dout_set.set(self.pin_mask);
+        let registers = &*self.registers;
+        registers.dout_set.set(self.pin_mask);
     }
 
     fn clear(&self) {
-        let regs = &*self.registers;
-        regs.dout_clr.set(self.pin_mask);
+        let registers = &*self.registers;
+        registers.dout_clr.set(self.pin_mask);
     }
 
     fn toggle(&self) {
-        let regs = &*self.registers;
-        regs.dout_tgl.set(self.pin_mask);
+        let registers = &*self.registers;
+        registers.dout_tgl.set(self.pin_mask);
     }
 
     fn read(&self) -> bool {
-        let regs = &*self.registers;
-        regs.din.get() & self.pin_mask != 0
+        let registers = &*self.registers;
+        registers.din.get() & self.pin_mask != 0
     }
 
     fn enable_interrupt(&self, client_data: usize, mode: hil::gpio::InterruptMode) {
@@ -141,10 +141,10 @@ impl IndexMut<usize> for Port {
 
 impl Port {
     pub fn handle_interrupt(&self) {
-        let regs = GPIO_BASE;
-        let evflags = regs.evflags.get();
+        let registers = GPIO_BASE;
+        let evflags = registers.evflags.get();
         // Clear all interrupts by setting their bits to 1 in evflags
-        regs.evflags.set(evflags);
+        registers.evflags.set(evflags);
 
         // evflags indicate which pins has triggered an interrupt,
         // we need to call the respective handler for positive bit in evflags.