Merge #1926

1926: Prepare for 64 PMP config registers r=hudson-ayers a=alistair23

### Pull Request Overview

This PR was supposed to add support for 64 PMP config register on RISC-V now that it is supported by the spec.

Instead this patch has turned more info converting the riscv-csr library to use the new inline assembly macro and to allow dynamic array access to the RISC-V registers.

This PR does a few things:
 - Converts the PMP CSRs to an array (to allow simplifying the PMP code)
 - Uses the new inline assembly. Unfortunately Rust won't let use access CSR dynamically like we used to (see rust-lang/rust#73220) so we now have a giant if statement to see which one to access. I couldn't see any other way to make the value const.
 - We also implement the register functions on specific types (u32) instead of generics. This is because with generics we can't dynamically access arrays of CSRs with the inline assembly.
 - Finally we clean up some of the PMP code.

### Testing Strategy

None yet.

### TODO or Help Wanted

Comments please, this is uglier then I would like it to be.

### Documentation Updated

- [X] Updated the relevant files in `/docs`, or no updates are required.

### Formatting

- [X] Ran `make prepush`.


Co-authored-by: Alistair Francis <alistair.francis@wdc.com>

arch/rv32i/src/csr/mod.rs

@@ -23,26 +23,8 @@ pub struct CSR {
     pub minstret: ReadWriteRiscvCsr<u32, minstret::minstret::Register>,
     pub mcycleh: ReadWriteRiscvCsr<u32, mcycle::mcycleh::Register>,
     pub mcycle: ReadWriteRiscvCsr<u32, mcycle::mcycle::Register>,
-    pub pmpcfg0: ReadWriteRiscvCsr<u32, pmpconfig::pmpcfg::Register>,
-    pub pmpcfg1: ReadWriteRiscvCsr<u32, pmpconfig::pmpcfg::Register>,
-    pub pmpcfg2: ReadWriteRiscvCsr<u32, pmpconfig::pmpcfg::Register>,
-    pub pmpcfg3: ReadWriteRiscvCsr<u32, pmpconfig::pmpcfg::Register>,
-    pub pmpaddr0: ReadWriteRiscvCsr<u32, pmpaddr::pmpaddr::Register>,
-    pub pmpaddr1: ReadWriteRiscvCsr<u32, pmpaddr::pmpaddr::Register>,
-    pub pmpaddr2: ReadWriteRiscvCsr<u32, pmpaddr::pmpaddr::Register>,
-    pub pmpaddr3: ReadWriteRiscvCsr<u32, pmpaddr::pmpaddr::Register>,
-    pub pmpaddr4: ReadWriteRiscvCsr<u32, pmpaddr::pmpaddr::Register>,
-    pub pmpaddr5: ReadWriteRiscvCsr<u32, pmpaddr::pmpaddr::Register>,
-    pub pmpaddr6: ReadWriteRiscvCsr<u32, pmpaddr::pmpaddr::Register>,
-    pub pmpaddr7: ReadWriteRiscvCsr<u32, pmpaddr::pmpaddr::Register>,
-    pub pmpaddr8: ReadWriteRiscvCsr<u32, pmpaddr::pmpaddr::Register>,
-    pub pmpaddr9: ReadWriteRiscvCsr<u32, pmpaddr::pmpaddr::Register>,
-    pub pmpaddr10: ReadWriteRiscvCsr<u32, pmpaddr::pmpaddr::Register>,
-    pub pmpaddr11: ReadWriteRiscvCsr<u32, pmpaddr::pmpaddr::Register>,
-    pub pmpaddr12: ReadWriteRiscvCsr<u32, pmpaddr::pmpaddr::Register>,
-    pub pmpaddr13: ReadWriteRiscvCsr<u32, pmpaddr::pmpaddr::Register>,
-    pub pmpaddr14: ReadWriteRiscvCsr<u32, pmpaddr::pmpaddr::Register>,
-    pub pmpaddr15: ReadWriteRiscvCsr<u32, pmpaddr::pmpaddr::Register>,
+    pub pmpcfg: [ReadWriteRiscvCsr<u32, pmpconfig::pmpcfg::Register>; 4],
+    pub pmpaddr: [ReadWriteRiscvCsr<u32, pmpaddr::pmpaddr::Register>; 16],
     pub mie: ReadWriteRiscvCsr<u32, mie::mie::Register>,
     pub mscratch: ReadWriteRiscvCsr<u32, mscratch::mscratch::Register>,
     pub mepc: ReadWriteRiscvCsr<u32, mepc::mepc::Register>,
@@ -57,40 +39,22 @@ pub struct CSR {
 
 // Define the "addresses" of each CSR register.
 pub const CSR: &CSR = &CSR {
-    minstreth: ReadWriteRiscvCsr::new(0xB82),
-    minstret: ReadWriteRiscvCsr::new(0xB02),
-    mcycleh: ReadWriteRiscvCsr::new(0xB80),
-    mcycle: ReadWriteRiscvCsr::new(0xB00),
-    mie: ReadWriteRiscvCsr::new(0x304),
-    mtvec: ReadWriteRiscvCsr::new(0x305),
-    mstatus: ReadWriteRiscvCsr::new(0x300),
-    utvec: ReadWriteRiscvCsr::new(0x005),
-    stvec: ReadWriteRiscvCsr::new(0x105),
-    mscratch: ReadWriteRiscvCsr::new(0x340),
-    mepc: ReadWriteRiscvCsr::new(0x341),
-    mcause: ReadWriteRiscvCsr::new(0x342),
-    mtval: ReadWriteRiscvCsr::new(0x343),
-    mip: ReadWriteRiscvCsr::new(0x344),
-    pmpcfg0: ReadWriteRiscvCsr::new(0x3A0),
-    pmpcfg1: ReadWriteRiscvCsr::new(0x3A1),
-    pmpcfg2: ReadWriteRiscvCsr::new(0x3A2),
-    pmpcfg3: ReadWriteRiscvCsr::new(0x3A3),
-    pmpaddr0: ReadWriteRiscvCsr::new(0x3B0),
-    pmpaddr1: ReadWriteRiscvCsr::new(0x3B1),
-    pmpaddr2: ReadWriteRiscvCsr::new(0x3B2),
-    pmpaddr3: ReadWriteRiscvCsr::new(0x3B3),
-    pmpaddr4: ReadWriteRiscvCsr::new(0x3B4),
-    pmpaddr5: ReadWriteRiscvCsr::new(0x3B5),
-    pmpaddr6: ReadWriteRiscvCsr::new(0x3B6),
-    pmpaddr7: ReadWriteRiscvCsr::new(0x3B7),
-    pmpaddr8: ReadWriteRiscvCsr::new(0x3B8),
-    pmpaddr9: ReadWriteRiscvCsr::new(0x3B9),
-    pmpaddr10: ReadWriteRiscvCsr::new(0x3BA),
-    pmpaddr11: ReadWriteRiscvCsr::new(0x3BB),
-    pmpaddr12: ReadWriteRiscvCsr::new(0x3BC),
-    pmpaddr13: ReadWriteRiscvCsr::new(0x3BD),
-    pmpaddr14: ReadWriteRiscvCsr::new(0x3BE),
-    pmpaddr15: ReadWriteRiscvCsr::new(0x3BF),
+    minstreth: ReadWriteRiscvCsr::new(riscv_csr::csr::MINSTRETH),
+    minstret: ReadWriteRiscvCsr::new(riscv_csr::csr::MINSTRET),
+    mcycleh: ReadWriteRiscvCsr::new(riscv_csr::csr::MCYCLEH),
+    mcycle: ReadWriteRiscvCsr::new(riscv_csr::csr::MCYCLE),
+    mie: ReadWriteRiscvCsr::new(riscv_csr::csr::MIE),
+    mtvec: ReadWriteRiscvCsr::new(riscv_csr::csr::MTVEC),
+    mstatus: ReadWriteRiscvCsr::new(riscv_csr::csr::MSTATUS),
+    utvec: ReadWriteRiscvCsr::new(riscv_csr::csr::UTVEC),
+    stvec: ReadWriteRiscvCsr::new(riscv_csr::csr::STVEC),
+    mscratch: ReadWriteRiscvCsr::new(riscv_csr::csr::MSCRATCH),
+    mepc: ReadWriteRiscvCsr::new(riscv_csr::csr::MEPC),
+    mcause: ReadWriteRiscvCsr::new(riscv_csr::csr::MCAUSE),
+    mtval: ReadWriteRiscvCsr::new(riscv_csr::csr::MTVAL),
+    mip: ReadWriteRiscvCsr::new(riscv_csr::csr::MIP),
+    pmpcfg: [ReadWriteRiscvCsr::new(riscv_csr::csr::PMPCFG0); 4],
+    pmpaddr: [ReadWriteRiscvCsr::new(riscv_csr::csr::PMPADDR0); 16],
 };
 
 impl CSR {