doc: add OT WG notes

doc/wg/opentitan/notes/2020-04-23.md

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+# Tock OT Notes 4/23/2020
+
+Present:
+- Brad Campbell (Chair), University of Virginia
+- Jon Flatley, Google
+- Silvestrs Timofejevs, lowRISC
+- Johnathan Van Why, Google
+- Garret Kelly, Google
+- Alistair Francis, Western Digital
+- Phil Levis, Stanford
+
+## Updates
+
+- Silvestrs: Starting to use OT DIFs with Tock. UART worked well. Had to add to
+  build.rs for linking.
+- Also working on conditional compilation. So far cargo cfgs seems like the best
+  approach.
+
+## Tock 1.5
+
+- Brad: Release testing is in progress.
+- Alistair: I've been testing apps, most don't work on OT.
+  - Some inlcude ARM assembly.
+  - Many libtock-c apps crash.
+  - Some multiple apps do work.
+- Long strings seem to be a problem (see issue). Something with hardware
+  configuration and reboot.
+- PMP doesn't need power of 2 rounding since using ToR.
+- Garret: So far only limited PMP support in OT.
+- Brad: We can mark OT support as preliminary.
+- Alistair: Should we test HiFive1?
+- Brad: I will.
+
+## Use Partial Crates
+
+- Silvestrs: can rust compile only certain files from a crate? Such that we can
+  substitute one peripheral for another?
+- Garret: I'm not sure. You likely can use a cfg in mod.rs to control what is
+  included in the compilation.
+- Silvestrs: Also, how does the lowrisc/ibex crate split work?
+- Alistair: Implementations of peripherals can be shared among multiple cores
+  (ibex being one example).
+- Brad: Modeled after SiFive structure.
+- Alistair: Some things may be in the wrong directory currently, which could
+  lead to confusion.
+
+## HMAC
+
+- Alistair: Not many changes.
+- Phil: Variable key lengths would have to be an async operation.
+- Jon: FIFO full not FIFO empty.
+- Alistair: Does that work?
+- Jon: Changed, I haven't tested.
+
+## Testing
+
+- Garret: Talked to Vadim. Questions about host testing. What is the hook point
+  for code to interface with hardware abstractions? They are using
+  `dev_mem_read()` and `dev_mem_write()` as a hook for testing.
+- Alistair: Can QEMU be used?
+- Garret: Not all peripherals are in QEMU. This is also heavy weight and
+  difficult to keep in sync with changing hardware until tape-out.
+- Higher level would apply more broadly, QEMU after tape-out maybe.
+- Alistair: Well if you are already writing models.
+- Garret: I still think it would be lower impact.

doc/wg/opentitan/notes/2020-04-30.md

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+# Tock OT Notes 4/30/2020
+
+Present:
+- Brad Campbell (Chair), University of Virginia
+- Jon Flatley, Google
+- Silvestrs Timofejevs, lowRISC
+- Johnathan Van Why, Google
+- Garret Kelly, Google
+- Alistair Francis, Western Digital
+- Phil Levis, Stanford
+
+
+## Updates
+
+- Silvestrs: Updated work on conditional compilation. Passes CI. Ready for
+  review.
+- Brad: Hopefully 1.5 will be merged today. Then can resume merging PRs.
+- Alistair: Working on OT and apps on QEMU. Goal: automated testing of PRs with
+  QEMU.
+- Sent out updates to QEMU on mailing list.
+  - Support for Ibex PLIC and UART, plus connecting those peripherals to the
+    main chip.
+- Garret: What does the maintenance look like for Ibex on QEMU? The chip is
+  changing, which version should QEMU match?
+- Alistair: UART is easy to keep up with any changes. Hopefully the PLIC becomes
+  standards compliant and therefore can use the default version.
+- Brad: Tested tock on Arty-e21 board, minor fixes needed but otherwise working
+  as expected.
+
+## PMP
+
+- Silvestrs: Why remove the "power of 2" check in the PMP implementation?
+- Alistair: That check is left over from the NAPOT implementation. With
+  Top-of-Range now it is not longer needed.
+- Garret: ToR for OT will require 32 byte alignment.
+- Alistair: I think that is standards compliant.
+- Brad: Using that as a default is probably fine, even if not required. Not a
+  huge overhead.
+
+- Phil: There might be alignment issues with memory protection more generally.
+- ARM has a standard, but some chips implemented their own version.
+- What is the outlook for PMP? Will we see a number of custom implementations?
+- Garret: I would expect that SiFive would stick the spec.
+- New RISC-V specs have been slow to be release, so I don't necessarily expect
+  it to change any time soon.
+- Alistair: Probably won't see a lot of custom implementations. Instead, there
+  may be spec extensions (like for the core) where peripherals like the PMP can
+  be customized but still standards compliant.
+- Garret: Well, OT is looking to use a non-compliant version that has additional
+  lock bits.
+- Phil: ARM you have to buy IP, presents a barrier.
+- Alistair: I think with RISC-V the trademark restriction would make it so a
+  non-spec version couldn't be called "RISC-V".
+- Garret: But the PMP is optional, so it could be a RISC-V core without a PMP,
+  and instead has an "OTPMP" which is different.
+- Garret: PMP currently too restrictive. Only 16 regions (8 effectively for
+  ToR). Use 6 regions for secure boot, not enough remaining.
+- Alistair: What about the extended PMP spec?
+- Garret: Is that out?
+- What happens with the hardware diversity?
+- Brad: Probably have to just embrace it.
+- Garret: Tock abstractions help.
+- Brad: Tricky part is finding bugs twice.
+- Phil: With variations in hardware there isn't much we can do.
+
+## libtock-rs
+
+- Johnathan: Not much change.
+
+## OT PRs
+
+- Phil: Are they ready, just waiting for 1.5?
+- Alistair: Yes. Should be ready or close to ready.
+- Phil: OK I can take a look.
+
+## HMAC
+
+- Phil: Key size issue. If variable key size, then setting the key must be
+  asynchronous. To avoid that complexity, better to fix the size for now.
+- But, certain implementations could use DMA (or something) to set the key, so
+  this may still have to change.

doc/wg/opentitan/notes/2020-05-07.md

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+# Tock OT Notes 5/07/2020
+
+Present:
+- Brad Campbell (Chair), University of Virginia
+- Jon Flatley, Google
+- Silvestrs Timofejevs, lowRISC
+- Johnathan Van Why, Google
+- Garret Kelly, Google
+- Alistair Francis, Western Digital
+- Phil Levis, Stanford
+- Alphan Ulusoy, Google
+
+## Updates
+
+- Silvestrs: Downstream Tock updates
+  - https://github.com/lowRISC/opentitan/issues/2139
+
+- Alphan: Working on OT syscall latency. 3 PRs to Tock.
+- Brad: Do you have some sense of the improvement?
+- Alphan: 8-9x improvement. about 5000 down to 400 cycles
+- Don't set MPU if already configured. Use mapcell for stored state. Don't
+  collect debug info.
+- Brad: Some work on HiFive1b. Various updates needed in Tock to convert the rev
+  a board to the rev b.
+
+## Chrome OS Roadmap
+
+- Garret: Two chips, one that isn't OpenTitan, but an OT as well.
+- Vadim can present.
+- TODO: Garret will invite Vadim to present.
+
+## QEMU Testing
+
+- Alistair: Moving to rexpect (expect in Rust) for QEMU testing. PR open.
+- Brad: What tests do you see adding? Kernel and userspace?
+- Alistair: rexpect is very flexible. Should be able to support any tests.
+- Brad: What about user interactive tests?
+- Alistair: rexpect will be able to nicely handle that as well.
+
+## PRs
+
+- Phil: Re: one byte reads in OT UART, subtlety there not well documented.
+- Brad: Right, callbacks only from interrupt handlers not clear.
+- Brad: We did have a thought about using capabilities passed in from the
+  interrupt handler.
+- Johnathan: This has also appeared in libtock-rs.