cortex-m: Add missing ISB after CONTROL writes #1863
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According to the ARM ARM, an instruction synchronization barrier is requried after switching processor priviledge state: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dai0321a/BIHFJCAC.html In practice, most Cortex-M's have tiny instruction caches, so this hasn't bitten us yet, but we should still do the right thing in case this becomes an issue in the future.
alistair23
approved these changes
May 19, 2020
hudson-ayers
approved these changes
May 19, 2020
bradjc
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May 19, 2020
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In the Cortex-M processors, the omission of the ISB after writing to the CONTROL register does not cause a program error, apart from the issue that instructions could have been pre-fetched using the previous privilege level. The ISB instruction is only required if it is necessary to have the subsequent instructions fetched with the correct privilege level.
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bors r+ |
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Pull Request Overview
According to the ARM ARM, an instruction synchronization barrier is
requried after switching processor priviledge state:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dai0321a/BIHFJCAC.html
In practice, most Cortex-M's have tiny instruction caches, so this hasn't
bitten us yet, but we should still do the right thing in case this becomes
an issue in the future.
Testing Strategy
Compiling.
TODO or Help Wanted
Need to test on HW.
Documentation Updated
/docs, or no updates are required.Formatting
make format.make clippy.