chips: ibex: Enable low power state

chips/ibex/src/chip.rs

@@ -6,13 +6,15 @@ use core::hint::unreachable_unchecked;
 use kernel;
 use kernel::common::registers::FieldValue;
 use kernel::debug;
+use kernel::Chip;
 use rv32i::csr::{mcause, mie::mie, mip::mip, mtvec::mtvec, CSR};
 use rv32i::syscall::SysCall;
 
 use crate::gpio;
 use crate::hmac;
 use crate::interrupts;
 use crate::plic;
+use crate::pwrmgr;
 use crate::timer;
 use crate::uart;
 use crate::usbdev;
@@ -38,7 +40,7 @@ impl Ibex {
         plic::enable_all();
     }
 
-    unsafe fn handle_plic_interrupts() {
+    unsafe fn handle_plic_interrupts(&self) {
         while let Some(interrupt) = plic::next_pending() {
             match interrupt {
                 interrupts::UART_TX_WATERMARK..=interrupts::UART_RX_PARITY_ERR => {
@@ -54,11 +56,51 @@ impl Ibex {
                 interrupts::USBDEV_PKT_RECEIVED..=interrupts::USBDEV_CONNECTED => {
                     usbdev::USB.handle_interrupt()
                 }
+                interrupts::PWRMGRWAKEUP => {
+                    pwrmgr::PWRMGR.handle_interrupt();
+                    self.check_until_true_or_interrupt(
+                        || pwrmgr::PWRMGR.check_clock_propagation(),
+                        None,
+                    );
+                }
                 _ => debug!("Pidx {}", interrupt),
             }
             plic::complete(interrupt);
         }
     }
+
+    /// Run a function in an interruptable loop.
+    ///
+    /// The function will run until it returns true, an interrupt occurs or if
+    /// `max_tries` is not `None` and that limit is reached.
+    /// If the function returns true this call will also return true. If an
+    /// interrupt occurs or `max_tries` is reached this call will return false.
+    fn check_until_true_or_interrupt<F>(&self, f: F, max_tries: Option<usize>) -> bool
+    where
+        F: Fn() -> bool,
+    {
+        match max_tries {
+            Some(t) => {
+                for _i in 0..t {
+                    if self.has_pending_interrupts() {
+                        return false;
+                    }
+                    if f() {
+                        return true;
+                    }
+                }
+            }
+            None => {
+                while !self.has_pending_interrupts() {
+                    if f() {
+                        return true;
+                    }
+                }
+            }
+        }
+
+        false
+    }
 }
 
 impl kernel::Chip for Ibex {
@@ -92,7 +134,7 @@ impl kernel::Chip for Ibex {
             }
             if mip.is_set(mip::mext) {
                 unsafe {
-                    Self::handle_plic_interrupts();
+                    self.handle_plic_interrupts();
                 }
                 reenable_intr += mie::mext::SET;
             }
@@ -113,6 +155,8 @@ impl kernel::Chip for Ibex {
 
     fn sleep(&self) {
         unsafe {
+            pwrmgr::PWRMGR.enable_low_power();
+            self.check_until_true_or_interrupt(|| pwrmgr::PWRMGR.check_clock_propagation(), None);
             rv32i::support::wfi();
         }
     }

chips/ibex/src/interrupts.rs

@@ -2,6 +2,8 @@
 
 #![allow(dead_code)]
 
+pub const PWRMGRWAKEUP: u32 = 0x50;
+
 pub const USBDEV_CONNECTED: u32 = 0x4f;
 pub const USBDEV_FRAME: u32 = 0x4e;
 pub const USBDEV_RX_BITSTUFF_ERR: u32 = 0x4d;

chips/ibex/src/lib.rs

@@ -13,6 +13,7 @@ pub mod gpio;
 pub mod hmac;
 pub mod i2c;
 pub mod plic;
+pub mod pwrmgr;
 pub mod timer;
 pub mod uart;
 pub mod usbdev;

chips/ibex/src/pwrmgr.rs

@@ -0,0 +1,7 @@
+use kernel::common::StaticRef;
+use lowrisc::pwrmgr::{PwrMgr, PwrMgrRegisters};
+
+pub static mut PWRMGR: PwrMgr = PwrMgr::new(PWRMGR_BASE);
+
+const PWRMGR_BASE: StaticRef<PwrMgrRegisters> =
+    unsafe { StaticRef::new(0x400A_0000 as *const PwrMgrRegisters) };

chips/lowrisc/src/lib.rs

@@ -8,5 +8,6 @@
 pub mod gpio;
 pub mod hmac;
 pub mod i2c;
+pub mod pwrmgr;
 pub mod uart;
 pub mod usbdev;

chips/lowrisc/src/pwrmgr.rs

@@ -0,0 +1,110 @@
+//! Power Mangement for LowRISC
+
+use kernel::common::registers::{register_bitfields, register_structs, ReadOnly, ReadWrite};
+use kernel::common::StaticRef;
+
+register_structs! {
+    pub PwrMgrRegisters {
+        (0x00 => ctrl_cfg_regwen: ReadOnly<u32, CTRL_CFG_REGWEN::Register>),
+        (0x04 => control: ReadWrite<u32, CONTROL::Register>),
+        (0x08 => cfg_cdc_sync: ReadWrite<u32, CFG_CDC_SYNC::Register>),
+        (0x0C => wakeup_en_regwen: ReadWrite<u32, WAKEUP_EN_REGWEN::Register>),
+        (0x10 => wakeup_en: ReadWrite<u32, WAKEUP_EN::Register>),
+        (0x14 => wake_status: ReadOnly<u32, WAKE_STATUS::Register>),
+        (0x18 => reset_en_regwen: ReadWrite<u32, RESET_EN_REGWEN::Register>),
+        (0x1C => reset_en: ReadWrite<u32, RESET_EN::Register>),
+        (0x20 => reset_status: ReadOnly<u32, RESET_STATUS::Register>),
+        (0x24 => wake_info_capture_dis: ReadWrite<u32, WAKE_INFO_CAPTURE_DIS::Register>),
+        (0x28 => wake_info: ReadWrite<u32, WAKE_INFO::Register>),
+        (0x2C => @END),
+    }
+}
+
+register_bitfields![u32,
+    CTRL_CFG_REGWEN [
+        EN OFFSET(0) NUMBITS(1) []
+    ],
+    CONTROL [
+        LOW_POWER_HINT OFFSET(0) NUMBITS(1) [],
+        CORE_CLK_EN OFFSET(4) NUMBITS(1) [],
+        IO_CLK_EN OFFSET(5) NUMBITS(1) [],
+        MAIN_PD_N OFFSET(6) NUMBITS(1) []
+    ],
+    CFG_CDC_SYNC [
+        SYNC OFFSET(0) NUMBITS(1) []
+    ],
+    WAKEUP_EN_REGWEN [
+        EN OFFSET(0) NUMBITS(1) []
+    ],
+    WAKEUP_EN [
+        START OFFSET(0) NUMBITS(16) []
+    ],
+    WAKE_STATUS [
+        VAL OFFSET(0) NUMBITS(16) []
+    ],
+    RESET_EN_REGWEN [
+        EN OFFSET(0) NUMBITS(1) []
+    ],
+    RESET_EN [
+        EN OFFSET(0) NUMBITS(2) []
+    ],
+    RESET_STATUS [
+        VAL OFFSET(0) NUMBITS(2) []
+    ],
+    WAKE_INFO_CAPTURE_DIS [
+        VAL OFFSET(0) NUMBITS(1) []
+    ],
+    WAKE_INFO [
+        REASONS OFFSET(0) NUMBITS(16) [],
+        FALL_THROUGH OFFSET(16) NUMBITS(1) [],
+        ABORT OFFSET(17) NUMBITS(1) []
+    ]
+];
+
+pub struct PwrMgr {
+    registers: StaticRef<PwrMgrRegisters>,
+}
+
+impl PwrMgr {
+    pub const fn new(base: StaticRef<PwrMgrRegisters>) -> PwrMgr {
+        PwrMgr { registers: base }
+    }
+
+    pub fn check_clock_propagation(&self) -> bool {
+        let regs = self.registers;
+
+        if regs.cfg_cdc_sync.read(CFG_CDC_SYNC::SYNC) == 0 {
+            return true;
+        }
+
+        false
+    }
+
+    pub fn handle_interrupt(&self) {
+        let regs = self.registers;
+
+        // Disable power saving
+        regs.control.write(CONTROL::LOW_POWER_HINT::CLEAR);
+
+        // Propagate changes to slow clock domain
+        regs.cfg_cdc_sync.write(CFG_CDC_SYNC::SYNC::SET);
+    }
+
+    pub fn enable_low_power(&self) {
+        let regs = self.registers;
+
+        if regs.control.read(CONTROL::LOW_POWER_HINT) != 1 {
+            // Next WFI should trigger low power entry
+            // Leave the IO clock enabled as we need to get interrupts
+            regs.control.write(
+                CONTROL::LOW_POWER_HINT::SET
+                    + CONTROL::CORE_CLK_EN::CLEAR
+                    + CONTROL::IO_CLK_EN::SET
+                    + CONTROL::MAIN_PD_N::CLEAR,
+            );
+
+            // Propagate changes to slow clock domain
+            regs.cfg_cdc_sync.write(CFG_CDC_SYNC::SYNC::SET);
+        }
+    }
+}