PhD student at Ben Gurion University, Israel. I'm occasionally uploading spare time projects to this github page - feel free to use the source codes :)
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FIR-filter
FIR-filter PublicSystemVerilog implementation of generalized FIR filter module and TB
SystemVerilog 2
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SDRAM-controller
SDRAM-controller PublicSDRAM controller implemented in SystemVerilog for ISSI IS42S16320f-7 IC
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