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DMA - Base Register Byte #27

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taylorza opened this issue Feb 20, 2022 · 2 comments
Closed

DMA - Base Register Byte #27

taylorza opened this issue Feb 20, 2022 · 2 comments
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bug To be fixed asap

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@taylorza
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zx-next-dev-guide/chapter-next-dma.tex

Line 870 in b724fbf

\item[{\tt 0}] \DMAPinLabel{CE}/\DMAPinLabel{WAIT} line functions only as chip enable line, allowing CPU to read and write control and status bytes when DMA is not owning the.

The above sentence ends abruptly with "... owning the.", this should probably be "... owning the bus"
@tomaz tomaz added the bug To be fixed asap label Feb 21, 2022
@tomaz
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tomaz commented Feb 21, 2022

Thanks! That's likely copy/paste issue. Though I can't exclude my brain excitingly jumping to next section while leaving my hands to wrap up existing one by themselves 😇

tomaz added a commit that referenced this issue Jun 10, 2022
@tomaz
Fixed DMA WR5 bit 4 description #27
2ae0c26
@tomaz
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tomaz commented Jun 10, 2022

Finally got to fixing this, I have couple more things to do, then will prepare a refreshed release. Thanks again for reporting!

@tomaz tomaz closed this as completed Jun 10, 2022
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