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| .*.swp |
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| # Pano Logic Zero Client G2 Constraints File | ||
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| # VCCAUX is 2.5 Volts | ||
| CONFIG VCCAUX = "2.5"; | ||
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| # 25 MHz System Clock | ||
| NET "SYSCLK" LOC = Y13 | IOSTANDARD = LVCMOS33; | ||
| TIMESPEC TS_CLK = PERIOD "SYSCLK" 25 MHz HIGH 50%; | ||
| NET "SYSCLK" TNM_NET = SYSCLK; | ||
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| # Reset Signals | ||
| #NET "SYSRST_N" LOC = AB14 | IOSTANDARD = LVCMOS33; | ||
| #NET "RESET_OUT_N" LOC = AA6 | IOSTANDARD = LVCMOS33; | ||
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| # Power Management | ||
| #NET "SLEEP_REQ" LOC = C13 | IOSTANDARD = LVCMOS33; | ||
| #NET "POWER_SLEEP" LOC = C10 | IOSTANDARD = LVCMOS33; | ||
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| # USB Clock Generation | ||
| #NET "USB_RST_N" LOC = W11 | IOSTANDARD = LVCMOS33; | ||
| #NET "USB_CLK" LOC = W12 | IOSTANDARD = LVCMOS33; | ||
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| # Pano Button LED Output, Active High | ||
| #NET "LED_RED" LOC = E12 | IOSTANDARD = LVCMOS33; | ||
| #NET "LED_BLUE" LOC = H13 | IOSTANDARD = LVCMOS33; | ||
| #NET "LED_GREEN" LOC = F13 | IOSTANDARD = LVCMOS33; | ||
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| # Pano Button Input, Active Low | ||
| NET "PANO_BUTTON" LOC = H12 | IOSTANDARD = LVCMOS33; | ||
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| # DVI Common | ||
| NET "V_SPD" LOC = D9 | IOSTANDARD = LVCMOS33; | ||
| NET "V_SPC" LOC = E8 | IOSTANDARD = LVCMOS33; | ||
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| # DVI Interface 1 (DVI) | ||
| NET "V1_D[0]" LOC = D17 | IOSTANDARD = LVCMOS33; | ||
| NET "V1_D[1]" LOC = A14 | IOSTANDARD = LVCMOS33; | ||
| NET "V1_D[2]" LOC = A15 | IOSTANDARD = LVCMOS33; | ||
| NET "V1_D[3]" LOC = A16 | IOSTANDARD = LVCMOS33; | ||
| NET "V1_D[4]" LOC = A17 | IOSTANDARD = LVCMOS33; | ||
| NET "V1_D[5]" LOC = A18 | IOSTANDARD = LVCMOS33; | ||
| NET "V1_D[6]" LOC = D14 | IOSTANDARD = LVCMOS33; | ||
| NET "V1_D[7]" LOC = B14 | IOSTANDARD = LVCMOS33; | ||
| NET "V1_D[8]" LOC = B16 | IOSTANDARD = LVCMOS33; | ||
| NET "V1_D[9]" LOC = B18 | IOSTANDARD = LVCMOS33; | ||
| NET "V1_D[10]" LOC = E16 | IOSTANDARD = LVCMOS33; | ||
| NET "V1_D[11]" LOC = D15 | IOSTANDARD = LVCMOS33; | ||
| NET "V1_XCLK_P" LOC = E14 | IOSTANDARD = LVCMOS33; | ||
| NET "V1_XCLK_N" LOC = F15 | IOSTANDARD = LVCMOS33; | ||
| NET "V1_HSYNC" LOC = F12 | IOSTANDARD = LVCMOS33; | ||
| NET "V1_VSYNC" LOC = C16 | IOSTANDARD = LVCMOS33; | ||
| NET "V1_DE" LOC = F14 | IOSTANDARD = LVCMOS33; | ||
| NET "V1_RESET_N" LOC = C15 | IOSTANDARD = LVCMOS33; | ||
| #NET "DDC1_SCK" LOC = C14 | IOSTANDARD = LVCMOS33; | ||
| #NET "DDC1_SDA" LOC = C17 | IOSTANDARD = LVCMOS33; | ||
| #NET "V1_HPINT" LOC = D13 | IOSTANDARD = LVCMOS33; # Hot-plug detect interrupt input, active low | ||
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| # DVI Interface 2 (micro-HDMI) | ||
| #NET "V2_D[0]" LOC = T18 | IOSTANDARD = LVCMOS33; | ||
| #NET "V2_D[1]" LOC = U16 | IOSTANDARD = LVCMOS33; | ||
| #NET "V2_D[2]" LOC = V17 | IOSTANDARD = LVCMOS33; | ||
| #NET "V2_D[3]" LOC = V19 | IOSTANDARD = LVCMOS33; | ||
| #NET "V2_D[4]" LOC = V18 | IOSTANDARD = LVCMOS33; | ||
| #NET "V2_D[5]" LOC = W17 | IOSTANDARD = LVCMOS33; | ||
| #NET "V2_D[6]" LOC = Y17 | IOSTANDARD = LVCMOS33; | ||
| #NET "V2_D[7]" LOC = Y15 | IOSTANDARD = LVCMOS33; | ||
| #NET "V2_D[8]" LOC = Y18 | IOSTANDARD = LVCMOS33; | ||
| #NET "V2_D[9]" LOC = Y19 | IOSTANDARD = LVCMOS33; | ||
| #NET "V2_D[10]" LOC = AB21 | IOSTANDARD = LVCMOS33; | ||
| #NET "V2_D[11]" LOC = T17 | IOSTANDARD = LVCMOS33; | ||
| #NET "V2_XCLK_P" LOC = T15 | IOSTANDARD = LVCMOS33; # Clock output | ||
| #NET "V2_HSYNC" LOC = AB15 | IOSTANDARD = LVCMOS33; # H-sync output | ||
| #NET "V2_VSYNC" LOC = T16 | IOSTANDARD = LVCMOS33; # V-sync output | ||
| #NET "V2_DE" LOC = AB16 | IOSTANDARD = LVCMOS33; # Data enable output | ||
| #NET "V2_RESET_N" LOC = W18 | IOSTANDARD = LVCMOS33; # Reset output, active low | ||
| #NET "DDC2_SCK" LOC = AA21 | IOSTANDARD = LVCMOS33; # Display data channel clock | ||
| #NET "DDC2_SDA" LOC = AB19 | IOSTANDARD = LVCMOS33; # Display data channel data | ||
| #NET "V2_HPINT" LOC = AB18 | IOSTANDARD = LVCMOS33; # Hot-plug detect interrupt input, active low | ||
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| # USB PHY | ||
| #NET "ULPI_DATA[7]" LOC = A4 | IOSTANDARD = LVCMOS33; | ||
| #NET "ULPI_DATA[6]" LOC = A6 | IOSTANDARD = LVCMOS33; | ||
| #NET "ULPI_DATA[5]" LOC = B6 | IOSTANDARD = LVCMOS33; | ||
| #NET "ULPI_DATA[4]" LOC = C6 | IOSTANDARD = LVCMOS33; | ||
| #NET "ULPI_DATA[3]" LOC = D6 | IOSTANDARD = LVCMOS33; | ||
| #NET "ULPI_DATA[2]" LOC = A8 | IOSTANDARD = LVCMOS33; | ||
| #NET "ULPI_DATA[1]" LOC = B8 | IOSTANDARD = LVCMOS33; | ||
| #NET "ULPI_DATA[0]" LOC = A7 | IOSTANDARD = LVCMOS33; | ||
| #NET "ULPI_NXT" LOC = C5 | IOSTANDARD = LVCMOS33; | ||
| #NET "ULPI_DIR" LOC = C7 | IOSTANDARD = LVCMOS33; | ||
| #NET "ULPI_STP" LOC = A5 | IOSTANDARD = LVCMOS33; | ||
| #NET "ULPI_60M_CLK" LOC = C12 | IOSTANDARD = LVCMOS33; | ||
| #NET "USB3300_RESET" LOC = C9 | IOSTANDARD = LVCMOS33; | ||
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| # Audio interface | ||
| #NET "ADC_BCLK" LOC = AB13 | IOSTANDARD = LVCMOS33; | ||
| #NET "ADC_ADCLRC" LOC = W9 | IOSTANDARD = LVCMOS33; | ||
| #NET "ADC_ADCDAT" LOC = R13 | IOSTANDARD = LVCMOS33; | ||
| #NET "ADC_DACLRC" LOC = U6 | IOSTANDARD = LVCMOS33; | ||
| #NET "ADC_DACDAT" LOC = Y14 | IOSTANDARD = LVCMOS33; | ||
| #NET "ADC_MCLK" LOC = W14 | IOSTANDARD = LVCMOS33; | ||
| #NET "ADC_SCLK" LOC = U17 | IOSTANDARD = LVCMOS33; | ||
| #NET "ADC_SDIN" LOC = AB17 | IOSTANDARD = LVCMOS33; | ||
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| # Ethernet PHY | ||
| #NET "GMII_TX_DATA[7]" LOC = Y10 | IOSTANDARD = LVCMOS33; | ||
| #NET "GMII_TX_DATA[6]" LOC = T7 | IOSTANDARD = LVCMOS33; | ||
| #NET "GMII_TX_DATA[5]" LOC = AB10 | IOSTANDARD = LVCMOS33; | ||
| #NET "GMII_TX_DATA[4]" LOC = AB9 | IOSTANDARD = LVCMOS33; | ||
| #NET "GMII_TX_DATA[3]" LOC = AB7 | IOSTANDARD = LVCMOS33; | ||
| #NET "GMII_TX_DATA[2]" LOC = AB4 | IOSTANDARD = LVCMOS33; | ||
| #NET "GMII_TX_DATA[1]" LOC = AB3 | IOSTANDARD = LVCMOS33; | ||
| #NET "GMII_TX_DATA[0]" LOC = AB2 | IOSTANDARD = LVCMOS33; | ||
| #NET "GMII_TX_CLK" LOC = Y11 | IOSTANDARD = LVCMOS33; | ||
| #NET "GMII_TX_ER" LOC = AB8 | IOSTANDARD = LVCMOS33; # NC | ||
| #NET "GMII_TX_EN" LOC = AA8 | IOSTANDARD = LVCMOS33; | ||
| #NET "MII_GMII_MDIO" LOC = AA2 | IOSTANDARD = LVCMOS33; | ||
| #NET "MII_GMII_MDC" LOC = AB6 | IOSTANDARD = LVCMOS33; | ||
| #NET "GMII_RST_N" LOC = R11 | IOSTANDARD = LVCMOS33; | ||
| #NET "GTX_CLK" LOC = AA12 | IOSTANDARD = LVCMOS33; | ||
| #NET "GMII_RX_DATA[7]" LOC = Y9 | IOSTANDARD = LVCMOS33; | ||
| #NET "GMII_RX_DATA[6]" LOC = U9 | IOSTANDARD = LVCMOS33; | ||
| #NET "GMII_RX_DATA[5]" LOC = R8 | IOSTANDARD = LVCMOS33; | ||
| #NET "GMII_RX_DATA[4]" LOC = V9 | IOSTANDARD = LVCMOS33; | ||
| #NET "GMII_RX_DATA[3]" LOC = R7 | IOSTANDARD = LVCMOS33; | ||
| #NET "GMII_RX_DATA[2]" LOC = R9 | IOSTANDARD = LVCMOS33; | ||
| #NET "GMII_RX_DATA[1]" LOC = Y4 | IOSTANDARD = LVCMOS33; | ||
| #NET "GMII_RX_DATA[0]" LOC = Y3 | IOSTANDARD = LVCMOS33; | ||
| #NET "GMII_RX_ER" LOC = Y8 | IOSTANDARD = LVCMOS33; | ||
| #NET "GMII_RX_DV" LOC = Y7 | IOSTANDARD = LVCMOS33; | ||
| #NET "GMII_RX_CLK" LOC = AB11 | IOSTANDARD = LVCMOS33; | ||
| #NET "GMII_COL" LOC = V7 | IOSTANDARD = LVCMOS33; | ||
| #NET "GMII_CRS" LOC = W4 | IOSTANDARD = LVCMOS33; | ||
| #NET "ENET_LINK_ACTIVE_N" LOC = AA4 | IOSTANDARD = LVCMOS33; | ||
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| # DDR2 SDRAM Interface A | ||
| #NET "DDR2A_D[0]" LOC = N20 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2A_D[1]" LOC = N22 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2A_D[2]" LOC = M21 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2A_D[3]" LOC = M22 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2A_D[4]" LOC = J20 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2A_D[5]" LOC = J22 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2A_D[6]" LOC = K21 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2A_D[7]" LOC = K22 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2A_D[8]" LOC = P21 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2A_D[9]" LOC = P22 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2A_D[10]" LOC = R20 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2A_D[11]" LOC = R22 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2A_D[12]" LOC = U20 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2A_D[13]" LOC = U22 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2A_D[14]" LOC = V21 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2A_D[15]" LOC = V22 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2A_CKE" LOC = D21 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2A_A[12]" LOC = D22 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2A_A[11]" LOC = F19 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2A_A[10]" LOC = G19 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2A_A[9]" LOC = C22 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2A_A[8]" LOC = C20 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2A_A[7]" LOC = E20 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2A_A[6]" LOC = K19 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2A_A[5]" LOC = K20 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2A_A[4]" LOC = F20 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2A_A[3]" LOC = G20 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2A_A[2]" LOC = E22 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2A_A[1]" LOC = F22 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2A_A[0]" LOC = F21 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2A_BA[2]" LOC = H18 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2A_BA[1]" LOC = K17 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2A_BA[0]" LOC = J17 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2A_RAS_L" LOC = H21 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2A_CAS_L" LOC = H22 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2A_WE_L" LOC = H19 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2A_CK_P" LOC = H20 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2A_CK_N" LOC = J19 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2A_ODT" LOC = G22 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2A_UDM" LOC = M20 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2A_LDM" LOC = L19 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2A_LDQS_P" LOC = L20 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2A_LDQS_N" LOC = L22 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2A_UDQS_P" LOC = T21 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2A_UDQS_N" LOC = T22 | IOSTANDARD = LVCMOS18; | ||
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| # DDR2 SDRAM Interface B | ||
| #NET "DDR2B_D[15]" LOC = V1 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2B_D[14]" LOC = V2 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2B_D[13]" LOC = U1 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2B_D[12]" LOC = U3 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2B_D[11]" LOC = R1 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2B_D[10]" LOC = R3 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2B_D[9]" LOC = P1 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2B_D[8]" LOC = P2 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2B_D[7]" LOC = K1 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2B_D[6]" LOC = K2 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2B_D[5]" LOC = J1 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2B_D[4]" LOC = J3 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2B_D[3]" LOC = M1 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2B_D[2]" LOC = M2 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2B_D[1]" LOC = N1 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2B_D[0]" LOC = N3 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2B_CKE" LOC = D2 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2B_A[12]" LOC = D1 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2B_A[11]" LOC = C1 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2B_A[10]" LOC = G4 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2B_A[9]" LOC = E1 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2B_A[8]" LOC = E3 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2B_A[7]" LOC = H6 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2B_A[6]" LOC = J4 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2B_A[5]" LOC = K3 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2B_A[4]" LOC = F3 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2B_A[3]" LOC = K6 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2B_A[2]" LOC = H5 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2B_A[1]" LOC = H1 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2B_A[0]" LOC = H2 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2B_BA[2]" LOC = F1 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2B_BA[1]" LOC = G1 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2B_BA[0]" LOC = G3 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2B_RAS_L" LOC = K5 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2B_CAS_L" LOC = K4 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2B_WE_L" LOC = F2 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2B_CK_P" LOC = H4 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2B_CK_N" LOC = H3 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2B_ODT" LOC = J6 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2B_UDM" LOC = M3 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2B_LDM" LOC = L4 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2B_LDQS_P" LOC = L3 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2B_LDQS_N" LOC = L1 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2B_UDQS_P" LOC = T2 | IOSTANDARD = LVCMOS18; | ||
| #NET "DDR2B_UDQS_N" LOC = T1 | IOSTANDARD = LVCMOS18; |
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| DVI Example. | ||
|
|
||
| Currently non-functional. |
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| * | ||
| */ |
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