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1. Computation-Storage-Design-and-Verification-using-Verilog-and-UVM Computation-Storage-Design-and-Verification-using-Verilog-and-UVM Public

   Build a UVM Environment for an a computation storage module, that does arithmetic operations where memory resides. Concepts like virtual sequencer, reset agents were used.

   Verilog

2. Synchronous-FIFO-Design-and-Verification-using-Verilog-and-UVM Synchronous-FIFO-Design-and-Verification-using-Verilog-and-UVM Public

   Build a UVM Environment for an a Synchronous FIFO. Concepts like virtual sequencer, reset agents, assertions were used.

   Verilog 1

3. Universal-Asynchronous-Receiver-Transmitter-UART Universal-Asynchronous-Receiver-Transmitter-UART Public

   Implemented UART TX and RX Modules Using Verilog HDL. The RX Module uses the oversampling scheme in order to estimate the middle points of the transmitted bits and retrieve these points accordingly

   Verilog 1

4. Memory-Verification-using-UVM Memory-Verification-using-UVM Public

   Build a UVM Environment for an parametrized memory module, including uvm testbench architecture components such as; sequencer, driver, monitor, scoreboard and subscriber. design was verified using …

   SystemVerilog 1

5. ALU-Verification-using-SystemVerilog ALU-Verification-using-SystemVerilog Public

   Build a SystemVerilog Environment for an ALU, using OOP testbench components as; stimulus generator, driver, monitor, scoreboard. ALU was verified using QuestaSim.

   SystemVerilog 5