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clk: tegra: SDMMC controllers are on APB
Since the SDMMC controller registers are accessed via the APB, the APB must be flushed before gating the SDMMC clocks to prevent register accesses to the SDMMC controllers after their clocks are gated. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
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