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powerpc: introduce the ePAPR embedded hypervisor vmpic driver
The Freescale ePAPR reference hypervisor provides interrupt controller services via a hypercall interface, instead of emulating the MPIC controller. This is called the VMPIC. The ePAPR "virtual interrupt controller" provides interrupt controller services for external interrupts. External interrupts received by a partition can come from two sources: - Hardware interrupts - hardware interrupts come from external interrupt lines or on-chip I/O devices. - Virtual interrupts - virtual interrupts are generated by the hypervisor as part of some hypervisor service or hypervisor-created virtual device. Both types of interrupts are processed using the same programming model and same set of hypercalls. Signed-off-by: Ashish Kalra <ashish.kalra@freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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/* | ||
* EHV_PIC private definitions and structure. | ||
* | ||
* Copyright 2008-2010 Freescale Semiconductor, Inc. | ||
* | ||
* This file is licensed under the terms of the GNU General Public License | ||
* version 2. This program is licensed "as is" without any warranty of any | ||
* kind, whether express or implied. | ||
*/ | ||
#ifndef __EHV_PIC_H__ | ||
#define __EHV_PIC_H__ | ||
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#include <linux/irq.h> | ||
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#define NR_EHV_PIC_INTS 1024 | ||
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#define EHV_PIC_INFO(name) EHV_PIC_##name | ||
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#define EHV_PIC_VECPRI_POLARITY_NEGATIVE 0 | ||
#define EHV_PIC_VECPRI_POLARITY_POSITIVE 1 | ||
#define EHV_PIC_VECPRI_SENSE_EDGE 0 | ||
#define EHV_PIC_VECPRI_SENSE_LEVEL 0x2 | ||
#define EHV_PIC_VECPRI_POLARITY_MASK 0x1 | ||
#define EHV_PIC_VECPRI_SENSE_MASK 0x2 | ||
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struct ehv_pic { | ||
/* The remapper for this EHV_PIC */ | ||
struct irq_host *irqhost; | ||
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/* The "linux" controller struct */ | ||
struct irq_chip hc_irq; | ||
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/* core int flag */ | ||
int coreint_flag; | ||
}; | ||
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void ehv_pic_init(void); | ||
unsigned int ehv_pic_get_irq(void); | ||
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#endif /* __EHV_PIC_H__ */ |
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@@ -78,6 +78,10 @@ config MPIC | |
bool | ||
default n | ||
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config PPC_EPAPR_HV_PIC | ||
bool | ||
default n | ||
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config MPIC_WEIRD | ||
bool | ||
default n | ||
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/* | ||
* Driver for ePAPR Embedded Hypervisor PIC | ||
* | ||
* Copyright 2008-2011 Freescale Semiconductor, Inc. | ||
* | ||
* Author: Ashish Kalra <ashish.kalra@freescale.com> | ||
* | ||
* This file is licensed under the terms of the GNU General Public License | ||
* version 2. This program is licensed "as is" without any warranty of any | ||
* kind, whether express or implied. | ||
*/ | ||
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#include <linux/types.h> | ||
#include <linux/kernel.h> | ||
#include <linux/init.h> | ||
#include <linux/irq.h> | ||
#include <linux/smp.h> | ||
#include <linux/interrupt.h> | ||
#include <linux/slab.h> | ||
#include <linux/spinlock.h> | ||
#include <linux/of.h> | ||
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#include <asm/io.h> | ||
#include <asm/irq.h> | ||
#include <asm/smp.h> | ||
#include <asm/machdep.h> | ||
#include <asm/ehv_pic.h> | ||
#include <asm/fsl_hcalls.h> | ||
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#include "../../../kernel/irq/settings.h" | ||
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static struct ehv_pic *global_ehv_pic; | ||
static DEFINE_SPINLOCK(ehv_pic_lock); | ||
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static u32 hwirq_intspec[NR_EHV_PIC_INTS]; | ||
static u32 __iomem *mpic_percpu_base_vaddr; | ||
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#define IRQ_TYPE_MPIC_DIRECT 4 | ||
#define MPIC_EOI 0x00B0 | ||
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/* | ||
* Linux descriptor level callbacks | ||
*/ | ||
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void ehv_pic_unmask_irq(struct irq_data *d) | ||
{ | ||
unsigned int src = virq_to_hw(d->irq); | ||
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ev_int_set_mask(src, 0); | ||
} | ||
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void ehv_pic_mask_irq(struct irq_data *d) | ||
{ | ||
unsigned int src = virq_to_hw(d->irq); | ||
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ev_int_set_mask(src, 1); | ||
} | ||
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void ehv_pic_end_irq(struct irq_data *d) | ||
{ | ||
unsigned int src = virq_to_hw(d->irq); | ||
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ev_int_eoi(src); | ||
} | ||
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void ehv_pic_direct_end_irq(struct irq_data *d) | ||
{ | ||
out_be32(mpic_percpu_base_vaddr + MPIC_EOI / 4, 0); | ||
} | ||
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int ehv_pic_set_affinity(struct irq_data *d, const struct cpumask *dest, | ||
bool force) | ||
{ | ||
unsigned int src = virq_to_hw(d->irq); | ||
unsigned int config, prio, cpu_dest; | ||
int cpuid = irq_choose_cpu(dest); | ||
unsigned long flags; | ||
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spin_lock_irqsave(&ehv_pic_lock, flags); | ||
ev_int_get_config(src, &config, &prio, &cpu_dest); | ||
ev_int_set_config(src, config, prio, cpuid); | ||
spin_unlock_irqrestore(&ehv_pic_lock, flags); | ||
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return 0; | ||
} | ||
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static unsigned int ehv_pic_type_to_vecpri(unsigned int type) | ||
{ | ||
/* Now convert sense value */ | ||
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switch (type & IRQ_TYPE_SENSE_MASK) { | ||
case IRQ_TYPE_EDGE_RISING: | ||
return EHV_PIC_INFO(VECPRI_SENSE_EDGE) | | ||
EHV_PIC_INFO(VECPRI_POLARITY_POSITIVE); | ||
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case IRQ_TYPE_EDGE_FALLING: | ||
case IRQ_TYPE_EDGE_BOTH: | ||
return EHV_PIC_INFO(VECPRI_SENSE_EDGE) | | ||
EHV_PIC_INFO(VECPRI_POLARITY_NEGATIVE); | ||
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case IRQ_TYPE_LEVEL_HIGH: | ||
return EHV_PIC_INFO(VECPRI_SENSE_LEVEL) | | ||
EHV_PIC_INFO(VECPRI_POLARITY_POSITIVE); | ||
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case IRQ_TYPE_LEVEL_LOW: | ||
default: | ||
return EHV_PIC_INFO(VECPRI_SENSE_LEVEL) | | ||
EHV_PIC_INFO(VECPRI_POLARITY_NEGATIVE); | ||
} | ||
} | ||
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int ehv_pic_set_irq_type(struct irq_data *d, unsigned int flow_type) | ||
{ | ||
unsigned int src = virq_to_hw(d->irq); | ||
struct irq_desc *desc = irq_to_desc(d->irq); | ||
unsigned int vecpri, vold, vnew, prio, cpu_dest; | ||
unsigned long flags; | ||
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if (flow_type == IRQ_TYPE_NONE) | ||
flow_type = IRQ_TYPE_LEVEL_LOW; | ||
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irq_settings_clr_level(desc); | ||
irq_settings_set_trigger_mask(desc, flow_type); | ||
if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) | ||
irq_settings_set_level(desc); | ||
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vecpri = ehv_pic_type_to_vecpri(flow_type); | ||
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spin_lock_irqsave(&ehv_pic_lock, flags); | ||
ev_int_get_config(src, &vold, &prio, &cpu_dest); | ||
vnew = vold & ~(EHV_PIC_INFO(VECPRI_POLARITY_MASK) | | ||
EHV_PIC_INFO(VECPRI_SENSE_MASK)); | ||
vnew |= vecpri; | ||
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/* | ||
* TODO : Add specific interface call for platform to set | ||
* individual interrupt priorities. | ||
* platform currently using static/default priority for all ints | ||
*/ | ||
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prio = 8; | ||
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ev_int_set_config(src, vecpri, prio, cpu_dest); | ||
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spin_unlock_irqrestore(&ehv_pic_lock, flags); | ||
return 0; | ||
} | ||
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static struct irq_chip ehv_pic_irq_chip = { | ||
.irq_mask = ehv_pic_mask_irq, | ||
.irq_unmask = ehv_pic_unmask_irq, | ||
.irq_eoi = ehv_pic_end_irq, | ||
.irq_set_type = ehv_pic_set_irq_type, | ||
}; | ||
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static struct irq_chip ehv_pic_direct_eoi_irq_chip = { | ||
.irq_mask = ehv_pic_mask_irq, | ||
.irq_unmask = ehv_pic_unmask_irq, | ||
.irq_eoi = ehv_pic_direct_end_irq, | ||
.irq_set_type = ehv_pic_set_irq_type, | ||
}; | ||
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/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */ | ||
unsigned int ehv_pic_get_irq(void) | ||
{ | ||
int irq; | ||
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BUG_ON(global_ehv_pic == NULL); | ||
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if (global_ehv_pic->coreint_flag) | ||
irq = mfspr(SPRN_EPR); /* if core int mode */ | ||
else | ||
ev_int_iack(0, &irq); /* legacy mode */ | ||
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if (irq == 0xFFFF) /* 0xFFFF --> no irq is pending */ | ||
return NO_IRQ; | ||
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/* | ||
* this will also setup revmap[] in the slow path for the first | ||
* time, next calls will always use fast path by indexing revmap | ||
*/ | ||
return irq_linear_revmap(global_ehv_pic->irqhost, irq); | ||
} | ||
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static int ehv_pic_host_match(struct irq_host *h, struct device_node *node) | ||
{ | ||
/* Exact match, unless ehv_pic node is NULL */ | ||
return h->of_node == NULL || h->of_node == node; | ||
} | ||
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static int ehv_pic_host_map(struct irq_host *h, unsigned int virq, | ||
irq_hw_number_t hw) | ||
{ | ||
struct ehv_pic *ehv_pic = h->host_data; | ||
struct irq_chip *chip; | ||
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/* Default chip */ | ||
chip = &ehv_pic->hc_irq; | ||
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if (mpic_percpu_base_vaddr) | ||
if (hwirq_intspec[hw] & IRQ_TYPE_MPIC_DIRECT) | ||
chip = &ehv_pic_direct_eoi_irq_chip; | ||
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irq_set_chip_data(virq, chip); | ||
/* | ||
* using handle_fasteoi_irq as our irq handler, this will | ||
* only call the eoi callback and suitable for the MPIC | ||
* controller which set ISR/IPR automatically and clear the | ||
* highest priority active interrupt in ISR/IPR when we do | ||
* a specific eoi | ||
*/ | ||
irq_set_chip_and_handler(virq, chip, handle_fasteoi_irq); | ||
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/* Set default irq type */ | ||
irq_set_irq_type(virq, IRQ_TYPE_NONE); | ||
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return 0; | ||
} | ||
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static int ehv_pic_host_xlate(struct irq_host *h, struct device_node *ct, | ||
const u32 *intspec, unsigned int intsize, | ||
irq_hw_number_t *out_hwirq, unsigned int *out_flags) | ||
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{ | ||
/* | ||
* interrupt sense values coming from the guest device tree | ||
* interrupt specifiers can have four possible sense and | ||
* level encoding information and they need to | ||
* be translated between firmware type & linux type. | ||
*/ | ||
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static unsigned char map_of_senses_to_linux_irqtype[4] = { | ||
IRQ_TYPE_EDGE_FALLING, | ||
IRQ_TYPE_EDGE_RISING, | ||
IRQ_TYPE_LEVEL_LOW, | ||
IRQ_TYPE_LEVEL_HIGH, | ||
}; | ||
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*out_hwirq = intspec[0]; | ||
if (intsize > 1) { | ||
hwirq_intspec[intspec[0]] = intspec[1]; | ||
*out_flags = map_of_senses_to_linux_irqtype[intspec[1] & | ||
~IRQ_TYPE_MPIC_DIRECT]; | ||
} else { | ||
*out_flags = IRQ_TYPE_NONE; | ||
} | ||
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return 0; | ||
} | ||
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static struct irq_host_ops ehv_pic_host_ops = { | ||
.match = ehv_pic_host_match, | ||
.map = ehv_pic_host_map, | ||
.xlate = ehv_pic_host_xlate, | ||
}; | ||
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void __init ehv_pic_init(void) | ||
{ | ||
struct device_node *np, *np2; | ||
struct ehv_pic *ehv_pic; | ||
int coreint_flag = 1; | ||
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np = of_find_compatible_node(NULL, NULL, "epapr,hv-pic"); | ||
if (!np) { | ||
pr_err("ehv_pic_init: could not find epapr,hv-pic node\n"); | ||
return; | ||
} | ||
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if (!of_find_property(np, "has-external-proxy", NULL)) | ||
coreint_flag = 0; | ||
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ehv_pic = kzalloc(sizeof(struct ehv_pic), GFP_KERNEL); | ||
if (!ehv_pic) { | ||
of_node_put(np); | ||
return; | ||
} | ||
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ehv_pic->irqhost = irq_alloc_host(np, IRQ_HOST_MAP_LINEAR, | ||
NR_EHV_PIC_INTS, &ehv_pic_host_ops, 0); | ||
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if (!ehv_pic->irqhost) { | ||
of_node_put(np); | ||
return; | ||
} | ||
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np2 = of_find_compatible_node(NULL, NULL, "fsl,hv-mpic-per-cpu"); | ||
if (np2) { | ||
mpic_percpu_base_vaddr = of_iomap(np2, 0); | ||
if (!mpic_percpu_base_vaddr) | ||
pr_err("ehv_pic_init: of_iomap failed\n"); | ||
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of_node_put(np2); | ||
} | ||
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ehv_pic->irqhost->host_data = ehv_pic; | ||
ehv_pic->hc_irq = ehv_pic_irq_chip; | ||
ehv_pic->hc_irq.irq_set_affinity = ehv_pic_set_affinity; | ||
ehv_pic->coreint_flag = coreint_flag; | ||
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global_ehv_pic = ehv_pic; | ||
irq_set_default_host(global_ehv_pic->irqhost); | ||
} |