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MIPS: SGI-IP27: clean up bridge access and header files
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Introduced bridge_read/bridge_write/bridge_set/bridge_clr for accessing
bridge register and get rid of volatile declarations. Also removed
all typedefs from arch/mips/include/asm/pci/bridge.h and cleaned up
language in arch/mips/pci/ops-bridge.c

Signed-off-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: James Hogan <jhogan@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
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@paulburton
Thomas Bogendoerfer authored and paulburton committed Feb 19, 2019
1 parent db0e7d4 commit a44d924
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Showing 5 changed files with 138 additions and 192 deletions.
202 changes: 89 additions & 113 deletions arch/mips/include/asm/pci/bridge.h
View file
Expand Up @@ -45,18 +45,21 @@

#ifndef __ASSEMBLY__

/*
* All accesses to bridge hardware registers must be done
* using 32-bit loads and stores.
*/
typedef u32 bridgereg_t;
#define ATE_V 0x01
#define ATE_CO 0x02
#define ATE_PREC 0x04
#define ATE_PREF 0x08
#define ATE_BAR 0x10

#define ATE_PFNSHIFT 12
#define ATE_TIDSHIFT 8
#define ATE_RMFSHIFT 48

typedef u64 bridge_ate_t;
#define mkate(xaddr, xid, attr) (((xaddr) & 0x0000fffffffff000ULL) | \
((xid)<<ATE_TIDSHIFT) | \
(attr))

/* pointers to bridge ATEs
* are always "pointer to volatile"
*/
typedef volatile bridge_ate_t *bridge_ate_p;
#define BRIDGE_INTERNAL_ATES 128

/*
* It is generally preferred that hardware registers on the bridge
Expand All @@ -65,7 +68,7 @@ typedef volatile bridge_ate_t *bridge_ate_p;
* Generated from Bridge spec dated 04oct95
*/

typedef volatile struct bridge_s {
struct bridge_regs {
/* Local Registers 0x000000-0x00FFFF */

/* standard widget configuration 0x000000-0x000057 */
Expand All @@ -86,114 +89,114 @@ typedef volatile struct bridge_s {
#define b_wid_tflush b_widget.w_tflush

/* bridge-specific widget configuration 0x000058-0x00007F */
bridgereg_t _pad_000058;
bridgereg_t b_wid_aux_err; /* 0x00005C */
bridgereg_t _pad_000060;
bridgereg_t b_wid_resp_upper; /* 0x000064 */
bridgereg_t _pad_000068;
bridgereg_t b_wid_resp_lower; /* 0x00006C */
bridgereg_t _pad_000070;
bridgereg_t b_wid_tst_pin_ctrl; /* 0x000074 */
bridgereg_t _pad_000078[2];
u32 _pad_000058;
u32 b_wid_aux_err; /* 0x00005C */
u32 _pad_000060;
u32 b_wid_resp_upper; /* 0x000064 */
u32 _pad_000068;
u32 b_wid_resp_lower; /* 0x00006C */
u32 _pad_000070;
u32 b_wid_tst_pin_ctrl; /* 0x000074 */
u32 _pad_000078[2];

/* PMU & Map 0x000080-0x00008F */
bridgereg_t _pad_000080;
bridgereg_t b_dir_map; /* 0x000084 */
bridgereg_t _pad_000088[2];
u32 _pad_000080;
u32 b_dir_map; /* 0x000084 */
u32 _pad_000088[2];

/* SSRAM 0x000090-0x00009F */
bridgereg_t _pad_000090;
bridgereg_t b_ram_perr; /* 0x000094 */
bridgereg_t _pad_000098[2];
u32 _pad_000090;
u32 b_ram_perr; /* 0x000094 */
u32 _pad_000098[2];

/* Arbitration 0x0000A0-0x0000AF */
bridgereg_t _pad_0000A0;
bridgereg_t b_arb; /* 0x0000A4 */
bridgereg_t _pad_0000A8[2];
u32 _pad_0000A0;
u32 b_arb; /* 0x0000A4 */
u32 _pad_0000A8[2];

/* Number In A Can 0x0000B0-0x0000BF */
bridgereg_t _pad_0000B0;
bridgereg_t b_nic; /* 0x0000B4 */
bridgereg_t _pad_0000B8[2];
u32 _pad_0000B0;
u32 b_nic; /* 0x0000B4 */
u32 _pad_0000B8[2];

/* PCI/GIO 0x0000C0-0x0000FF */
bridgereg_t _pad_0000C0;
bridgereg_t b_bus_timeout; /* 0x0000C4 */
u32 _pad_0000C0;
u32 b_bus_timeout; /* 0x0000C4 */
#define b_pci_bus_timeout b_bus_timeout

bridgereg_t _pad_0000C8;
bridgereg_t b_pci_cfg; /* 0x0000CC */
bridgereg_t _pad_0000D0;
bridgereg_t b_pci_err_upper; /* 0x0000D4 */
bridgereg_t _pad_0000D8;
bridgereg_t b_pci_err_lower; /* 0x0000DC */
bridgereg_t _pad_0000E0[8];
u32 _pad_0000C8;
u32 b_pci_cfg; /* 0x0000CC */
u32 _pad_0000D0;
u32 b_pci_err_upper; /* 0x0000D4 */
u32 _pad_0000D8;
u32 b_pci_err_lower; /* 0x0000DC */
u32 _pad_0000E0[8];
#define b_gio_err_lower b_pci_err_lower
#define b_gio_err_upper b_pci_err_upper

/* Interrupt 0x000100-0x0001FF */
bridgereg_t _pad_000100;
bridgereg_t b_int_status; /* 0x000104 */
bridgereg_t _pad_000108;
bridgereg_t b_int_enable; /* 0x00010C */
bridgereg_t _pad_000110;
bridgereg_t b_int_rst_stat; /* 0x000114 */
bridgereg_t _pad_000118;
bridgereg_t b_int_mode; /* 0x00011C */
bridgereg_t _pad_000120;
bridgereg_t b_int_device; /* 0x000124 */
bridgereg_t _pad_000128;
bridgereg_t b_int_host_err; /* 0x00012C */
u32 _pad_000100;
u32 b_int_status; /* 0x000104 */
u32 _pad_000108;
u32 b_int_enable; /* 0x00010C */
u32 _pad_000110;
u32 b_int_rst_stat; /* 0x000114 */
u32 _pad_000118;
u32 b_int_mode; /* 0x00011C */
u32 _pad_000120;
u32 b_int_device; /* 0x000124 */
u32 _pad_000128;
u32 b_int_host_err; /* 0x00012C */

struct {
bridgereg_t __pad; /* 0x0001{30,,,68} */
bridgereg_t addr; /* 0x0001{34,,,6C} */
u32 __pad; /* 0x0001{30,,,68} */
u32 addr; /* 0x0001{34,,,6C} */
} b_int_addr[8]; /* 0x000130 */

bridgereg_t _pad_000170[36];
u32 _pad_000170[36];

/* Device 0x000200-0x0003FF */
struct {
bridgereg_t __pad; /* 0x0002{00,,,38} */
bridgereg_t reg; /* 0x0002{04,,,3C} */
u32 __pad; /* 0x0002{00,,,38} */
u32 reg; /* 0x0002{04,,,3C} */
} b_device[8]; /* 0x000200 */

struct {
bridgereg_t __pad; /* 0x0002{40,,,78} */
bridgereg_t reg; /* 0x0002{44,,,7C} */
u32 __pad; /* 0x0002{40,,,78} */
u32 reg; /* 0x0002{44,,,7C} */
} b_wr_req_buf[8]; /* 0x000240 */

struct {
bridgereg_t __pad; /* 0x0002{80,,,88} */
bridgereg_t reg; /* 0x0002{84,,,8C} */
u32 __pad; /* 0x0002{80,,,88} */
u32 reg; /* 0x0002{84,,,8C} */
} b_rrb_map[2]; /* 0x000280 */
#define b_even_resp b_rrb_map[0].reg /* 0x000284 */
#define b_odd_resp b_rrb_map[1].reg /* 0x00028C */

bridgereg_t _pad_000290;
bridgereg_t b_resp_status; /* 0x000294 */
bridgereg_t _pad_000298;
bridgereg_t b_resp_clear; /* 0x00029C */
u32 _pad_000290;
u32 b_resp_status; /* 0x000294 */
u32 _pad_000298;
u32 b_resp_clear; /* 0x00029C */

bridgereg_t _pad_0002A0[24];
u32 _pad_0002A0[24];

char _pad_000300[0x10000 - 0x000300];

/* Internal Address Translation Entry RAM 0x010000-0x0103FF */
union {
bridge_ate_t wr; /* write-only */
u64 wr; /* write-only */
struct {
bridgereg_t _p_pad;
bridgereg_t rd; /* read-only */
u32 _p_pad;
u32 rd; /* read-only */
} hi;
} b_int_ate_ram[128];

char _pad_010400[0x11000 - 0x010400];

/* Internal Address Translation Entry RAM LOW 0x011000-0x0113FF */
struct {
bridgereg_t _p_pad;
bridgereg_t rd; /* read-only */
u32 _p_pad;
u32 rd; /* read-only */
} b_int_ate_ram_lo[128];

char _pad_011400[0x20000 - 0x011400];
Expand All @@ -212,7 +215,7 @@ typedef volatile struct bridge_s {
} f[8];
} b_type0_cfg_dev[8]; /* 0x020000 */

/* PCI Type 1 Configuration Space 0x028000-0x028FFF */
/* PCI Type 1 Configuration Space 0x028000-0x028FFF */
union { /* make all access sizes available. */
u8 c[0x1000 / 1];
u16 s[0x1000 / 2];
Expand All @@ -233,7 +236,7 @@ typedef volatile struct bridge_s {
u8 _pad_030007[0x04fff8]; /* 0x030008-0x07FFFF */

/* External Address Translation Entry RAM 0x080000-0x0FFFFF */
bridge_ate_t b_ext_ate_ram[0x10000];
u64 b_ext_ate_ram[0x10000];

/* Reserved 0x100000-0x1FFFFF */
char _pad_100000[0x200000-0x100000];
Expand All @@ -259,13 +262,13 @@ typedef volatile struct bridge_s {
u32 l[0x400000 / 4]; /* read-only */
u64 d[0x400000 / 8]; /* read-only */
} b_external_flash; /* 0xC00000 */
} bridge_t;
};

/*
* Field formats for Error Command Word and Auxiliary Error Command Word
* of bridge.
*/
typedef struct bridge_err_cmdword_s {
struct bridge_err_cmdword {
union {
u32 cmd_word;
struct {
Expand All @@ -282,15 +285,15 @@ typedef struct bridge_err_cmdword_s {
rsvd:8;
} berr_st;
} berr_un;
} bridge_err_cmdword_t;
};

#define berr_field berr_un.berr_st
#endif /* !__ASSEMBLY__ */

/*
* The values of these macros can and should be crosschecked
* regularly against the offsets of the like-named fields
* within the "bridge_t" structure above.
* within the bridge_regs structure above.
*/

/* Byte offset macros for Bridge internal registers */
Expand Down Expand Up @@ -797,46 +800,12 @@ typedef struct bridge_err_cmdword_s {
#define PCI64_ATTR_RMF_MASK 0x00ff000000000000
#define PCI64_ATTR_RMF_SHFT 48

#ifndef __ASSEMBLY__
/* Address translation entry for mapped pci32 accesses */
typedef union ate_u {
u64 ent;
struct ate_s {
u64 rmf:16;
u64 addr:36;
u64 targ:4;
u64 reserved:3;
u64 barrier:1;
u64 prefetch:1;
u64 precise:1;
u64 coherent:1;
u64 valid:1;
} field;
} ate_t;
#endif /* !__ASSEMBLY__ */

#define ATE_V 0x01
#define ATE_CO 0x02
#define ATE_PREC 0x04
#define ATE_PREF 0x08
#define ATE_BAR 0x10

#define ATE_PFNSHIFT 12
#define ATE_TIDSHIFT 8
#define ATE_RMFSHIFT 48

#define mkate(xaddr, xid, attr) ((xaddr) & 0x0000fffffffff000ULL) | \
((xid)<<ATE_TIDSHIFT) | \
(attr)

#define BRIDGE_INTERNAL_ATES 128

struct bridge_controller {
struct pci_controller pc;
struct resource mem;
struct resource io;
struct resource busn;
bridge_t *base;
struct bridge_regs *base;
nasid_t nasid;
unsigned int widget_id;
unsigned int irq_cpu;
Expand All @@ -847,6 +816,13 @@ struct bridge_controller {
#define BRIDGE_CONTROLLER(bus) \
((struct bridge_controller *)((bus)->sysdata))

#define bridge_read(bc, reg) __raw_readl(&bc->base->reg)
#define bridge_write(bc, reg, val) __raw_writel(val, &bc->base->reg)
#define bridge_set(bc, reg, val) \
__raw_writel(__raw_readl(&bc->base->reg) | (val), &bc->base->reg)
#define bridge_clr(bc, reg, val) \
__raw_writel(__raw_readl(&bc->base->reg) & ~(val), &bc->base->reg)

extern void register_bridge_irq(unsigned int irq);
extern int request_bridge_irq(struct bridge_controller *bc);

Expand Down
5 changes: 0 additions & 5 deletions arch/mips/include/asm/sn/sn0/addrs.h
View file
Expand Up @@ -134,11 +134,6 @@

#define CALIAS_BASE CAC_BASE



#define BRIDGE_REG_PTR(_base, _off) ((volatile bridgereg_t *) \
((__psunsigned_t)(_base) + (__psunsigned_t)(_off)))

#define SN0_WIDGET_BASE(_nasid, _wid) (NODE_SWIN_BASE((_nasid), (_wid)))

/* Turn on sable logging for the processors whose bits are set. */
Expand Down

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