feat: janky way of having tracing in ISRs #132
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; Conflicts: ; platforms/allwinner-d1/core/src/drivers/twi.rs
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jamesmunns
reviewed
Jul 6, 2023
| @@ -234,8 +234,10 @@ impl D1 { | |||
| /// At the moment, we only service the Channel 0 interrupt, | |||
| /// which indicates that the serial transmission is complete. | |||
| fn handle_dmac() { | |||
| let _isr = kernel::isr::Isr::enter(); | |||
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We could potentially do this at the top of the actual ISR entry point instead of in every handler
jamesmunns
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platform: D1
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This is not that good but it allows at least one ISR to trace even if
the interrupt fired while normal code was holding the trace WGR. We can
probably figure out a nicer version of this, with different tracebufs
for each ISR priority level, later.
Cherry-picked out of #103