Cycle accurate MC6502 compatible processor in Verilog.
This is an experimental project, and wasn't verified well. There will be many bugs and it will not meet practical use requirements.
rtl/
- MC6502 implementation
tb/
- Testbenches that can run with iverilog
third_party/
- git submodules, tvcl for simulation models
$ git submodule update --init
$ cd tb
$ make