tqma6ul: remove warning pragma for 512 MB variants

The RAM configs where prepared and simulated but could not be verified when starting production of the non LGA 512 MiB board variants. Therefore we added a warning which was not removed by accident when we finally qualified the mentioned LGA variants. Fix this. Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
tq-systems · Oct 14, 2022 · e89ae95 · e89ae95
1 parent 86a65bc
commit e89ae95
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diff --git a/board/tqc/tqma6ul/tqma6ul_512mb.cfg b/board/tqc/tqma6ul/tqma6ul_512mb.cfg
@@ -94,8 +94,6 @@ DATA 4 0x021B08C0 0x00921012	/* MMDC_MPDCCR MMDC Duty Cycle Control Register */
 
 #elif defined(CONFIG_TQMA6UL_VARIANT_LGA)
 
-#warning FIXME: no validated TQMa6ULxL 512 MB DDR timing yet
-
 DATA 4 0x021B080C 0x00000000	/* MMDC_MPWLDECTRL0 MMDC PHY Write Leveling Delay Control Register 0 */
 DATA 4 0x021B083C 0x41580150	/* MMDC_MPDGCTRL0 MMDC PHY Read DQS Gating Control Register 0 */
 DATA 4 0x021B0848 0x40404E52	/* MMDC_MPRDDLCTL MMDC PHY Read delay-lines Configuration Register */

diff --git a/board/tqc/tqma6ul/tqma6ull_512mb.cfg b/board/tqc/tqma6ul/tqma6ull_512mb.cfg
@@ -92,8 +92,6 @@ DATA 4 0x021B08C0 0x00921012	/* [MMDC_MPDCCR] MMDC Duty Cycle Control Register *
 
 #elif defined(CONFIG_TQMA6UL_VARIANT_LGA)
 
-#warning FIXME: no validated TQMa6ULLxL DDR timing yet
-
 DATA 4 0x021B080C 0x00050009	/* [MMDC_MPWLDECTRL0] MMDC PHY Write Leveling Delay Control Register 0 */
 DATA 4 0x021B083C 0x41340130	/* [MMDC_MPDGCTRL0] MMDC PHY Read DQS Gating Control Register 0 */
 DATA 4 0x021B0848 0x40403A3E	/* [MMDC_MPRDDLCTL] MMDC PHY Read delay-lines Configuration Register */