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Links
Miscellaneous links that I'll probably want to read again in the future.
DRAMA: Exploiting DRAM Addressing for Cross-CPU Attacks Description of physical -> DRAM mapping RE techniques, and results for many systems including Skylake DDR4. Uses a timing approach to find pairs of addresses that have a bank/row conflict. Associated github repo with the RE tool.
Ulrich Drepper's What Every Programmer Should Know About Memory
Sandy Bridge physical address to DRAM mapping well described. Note that Ivy Bridge is apparently more complex in the channel mapping.
Method for reverse engineering the physical-DRAM mapping describes how to determine the DRAM bank mappings by searching for bank collisions via timing.
Physical Address Decoding in Intel Xeon v3/v4 CPUs: A Supplemental Datasheet describes the physical to DRAM mapping down to rank granularity (socket, channel, rank, but not finder). They use a combination of a linear DRAM mapping and the normal interleaved mapping for the same region of DRAM, and then write a token using one mapping and search for it with the other, allowing exact determination of the interleaving function w/o any dependence on timing.
Descripiton of how to map offcore traffic counters to specific locations on the die, and a bit about the types of busses that are involved:
John McCalpin's description of how coherency works in KNL and Skylake-SP is excellent:
Topology and Cache Coherence in Knights Landing and Skylake Xeon Processors
The thesis Combining static and dynamic approaches to model loop performance in HPC has lots of good stuff in the appendices A and B, including methodologies for measuring the little-known load matrix size.