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According to datasheet: the following fields are incorrect: TMC5072_DC_TIME_MASK , TMC5072_DC_SG_MASK and TMC5072_DC_SG_SHIFT
Should be #define TMC5072_DC_TIME_MASK 0xFF // DCCTRL_M2 // Upper PWM on time limit for commutation (DC_TIME * 1/f CLK ). Set slightly above effective blank time TBL. #define TMC5072_DC_TIME_SHIFT 0 // min.: 0, max.: 1023, default: 0 #define TMC5072_DC_SG_MASK 0xFF00 // DCCTRL_M2 // Max. PWM on time for step loss detection using dcStep stallGuard2 in dcStep mode. (DC_SG * 16/f CLK); Set slightly higher than DC_TIME/16; 0=disable #define TMC5072_DC_SG_SHIFT 8 // min.: 0, max.: 255, default: 0
The text was updated successfully, but these errors were encountered:
Fixed - Thank you for the report 👍
Regards, Lenard
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According to datasheet:
the following fields are incorrect: TMC5072_DC_TIME_MASK , TMC5072_DC_SG_MASK and TMC5072_DC_SG_SHIFT
Should be
#define TMC5072_DC_TIME_MASK 0xFF // DCCTRL_M2 // Upper PWM on time limit for commutation (DC_TIME * 1/f CLK ). Set slightly above effective blank time TBL.
#define TMC5072_DC_TIME_SHIFT 0 // min.: 0, max.: 1023, default: 0
#define TMC5072_DC_SG_MASK 0xFF00 // DCCTRL_M2 // Max. PWM on time for step loss detection using dcStep stallGuard2 in dcStep mode. (DC_SG * 16/f CLK); Set slightly higher than DC_TIME/16; 0=disable
#define TMC5072_DC_SG_SHIFT 8 // min.: 0, max.: 255, default: 0
The text was updated successfully, but these errors were encountered: