add testbench for oled module

fix a few bugs in the oled module's startup sequence

oled_spi.v

@@ -6,18 +6,15 @@ module oled_spi(
   input wire reset,
   input wire shutdown,
 
-  output reg cs,
+  output wire cs,
   output reg sdin,
-  output reg sclk,
+  output wire sclk,
   output reg dc,
   output reg res,
   output reg vbatc,
   output reg vddc
 );
 
-  assign cs = 0;
-  assign sclk = !clock;
-
   parameter WAIT = 1;
   parameter SEND = 2;  // send 1 byte
   parameter SEND2 = 3; // send 2 bytes
@@ -61,6 +58,12 @@ module oled_spi(
       wait_max <= 32'b0;
       state <= STARTUP_1;
       next_state <= 1'b0;
+
+      sdin <= 1'b0;
+      dc <= 1'b0;
+      res <= 1'b1;
+      vddc <= 1'b1;
+      vbatc <= 1'b1;
     end
 
     // SHUTDOWN
@@ -130,20 +133,20 @@ module oled_spi(
       else if (state == STARTUP_2) begin
         send_buf <= 8'hAE;
         state <= SEND;
-        next_state <= STARTUP_2;
+        next_state <= STARTUP_3;
       end
 
       // STARTUP_3 -- clear screen
       else if (state == STARTUP_3) begin
-        rst <= 0;
+        res <= 0;
         wait_max <= 5000; // 1ms
         state <= WAIT;
         next_state <= STARTUP_4;
       end
 
       // STARTUP_4 -- set charge pump
       else if (state == STARTUP_4) begin
-        rst <= 1;
+        res <= 1;
         send_buf <= 16'h148D;
         state <= SEND2;
         next_state <= STARTUP_5;
@@ -207,5 +210,8 @@ module oled_spi(
       end
     end
   end
+
+  assign cs = 0;
+  assign sclk = !clock;
 
 endmodule

oled_spi_tb.v

@@ -0,0 +1,49 @@
+`default_nettype none
+`timescale 1ns / 1ps
+
+module oled_spi_tb;
+
+	// Inputs
+	reg clock;
+	reg reset;
+	reg shutdown;
+
+	// Outputs
+	wire cs;
+	wire sdin;
+	wire sclk;
+	wire dc;
+	wire res;
+	wire vbatc;
+	wire vddc;
+
+	// Instantiate the Unit Under Test (UUT)
+	oled_spi uut (
+		.clock(clock), 
+		.reset(reset), 
+		.shutdown(shutdown), 
+		.cs(cs), 
+		.sdin(sdin), 
+		.sclk(sclk), 
+		.dc(dc), 
+		.res(res), 
+		.vbatc(vbatc), 
+		.vddc(vddc)
+	);
+
+	initial begin
+		// Initialize Inputs
+		clock = 0;
+		reset = 1;
+		shutdown = 0;
+
+		// Wait 100 ns for global reset to finish
+		#100 reset = 0;
+	end
+
+  always begin
+    #10 clock = !clock;
+  end
+
+endmodule
+