Clean scrambler, lock, seq

ttchisholm · Apr 27, 2023 · 6c9bdb3 · 6c9bdb3
1 parent 410d4fe
commit 6c9bdb3
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Showing 6 changed files with 25 additions and 70 deletions.
diff --git a/src/hdl/pcs/descrambler.sv b/src/hdl/pcs/descrambler.sv
diff --git a/src/hdl/pcs/gearbox_seq.sv b/src/hdl/pcs/gearbox_seq.sv
@@ -38,4 +38,4 @@ module gearbox_seq #(
 
     assign pause = count == PAUSE_VAL;
 
-endmodule
+endmodule
diff --git a/src/hdl/pcs/lock_state.sv b/src/hdl/pcs/lock_state.sv
@@ -14,7 +14,9 @@ module lock_state(
         VALID_SH, INVALID_SH, GOOD_64, SLIP, X='x, Z='z} lock_state_t;
 
     lock_state_t state, next_state;
+    // verilator lint_off UNUSED
     logic rx_block_lock, test_sh, slip_done;
+    // verilator lint_on UNUSED
     logic [15:0] sh_cnt, sh_invalid_cnt;
     wire sh_valid;
 
@@ -54,12 +56,6 @@ module lock_state(
                 //              sh_cnt == 64 && sh_invalid_cnt != 0 ? RESET_CNT :
                 //              sh_cnt < 64 && !sh_valid ? INVALID_SH : VALID_SH;
 
-                // if (sh_cnt == 15'd10) begin
-                //     next_state = SLIP;
-                // end else begin
-                //     next_state = VALID_SH;
-                // end
-
                 if (!i_valid) begin
                     next_state = VALID_SH;
                 end if (sh_cnt == 64 && sh_invalid_cnt == 0) begin
@@ -147,4 +143,4 @@ module lock_state(
         end
     end
 
-endmodule
+endmodule
diff --git a/src/hdl/pcs/pcs.sv b/src/hdl/pcs/pcs.sv
@@ -74,14 +74,14 @@ module pcs #(
 
             // Delay the scrambler reset if 32-bit interface
             // TODO this only helps with tb?
-            logic scram_reset;
-            always @ (posedge xver_tx_clk)
-                scram_reset <= tx_reset;
+            // logic scram_reset;
+            // always @ (posedge xver_tx_clk)
+            //     scram_reset <= tx_reset;
 
             scrambler #(
             ) u_scrambler(
                 .clk(xver_tx_clk),
-                .reset(scram_reset),
+                .reset(tx_reset),
                 .init_done(!tx_reset),
                 .pause(tx_gearbox_pause),
                 .idata(tx_encoded_data),
@@ -157,8 +157,6 @@ module pcs #(
             assign rx_header_valid = xver_rx_header_valid;
 
         end else begin
-            wire [5:0] int_rx_gearbox_seq;
-            wire rx_gearbox_pause;
 
             rx_gearbox #(.REGISTER_OUTPUT(1)) 
             u_rx_gearbox (
@@ -237,4 +235,4 @@ module pcs #(
         term_loc <= early_term_loc;
     end
 
-endmodule
+endmodule
diff --git a/src/hdl/pcs/scrambler.sv b/src/hdl/pcs/scrambler.sv
@@ -2,8 +2,9 @@
 `default_nettype none
 
 module scrambler #(
-    localparam DATA_WIDTH = 32,
-    parameter DESCRAMBLE = 0
+    parameter DESCRAMBLE = 0, 
+
+    localparam DATA_WIDTH = 32
 ) (
     input wire clk,
     input wire reset,
@@ -13,8 +14,12 @@ module scrambler #(
     output wire [DATA_WIDTH-1:0] odata
 );
 
+    // verilator lint_off UNUSED
     logic[127:0] scrambler_data;
+    // verilator lint_on UNUSED
+
     logic [127:0] next_scrambler_data;
+    logic [95:0] next_scrambler_data_split;
 
     always @(posedge clk) begin
         if (reset || !init_done) begin
@@ -26,8 +31,13 @@ module scrambler #(
     end
 
     // Data here is reversed wrt. polynomial index
-    assign next_scrambler_data = DESCRAMBLE ? {{idata}, {scrambler_data[DATA_WIDTH +: 128 - DATA_WIDTH]}} :
-                                              {{odata}, {scrambler_data[DATA_WIDTH +: 128 - DATA_WIDTH]}};
+    // We need to split the scrambler data to avoid circular comb (verilator)
+    // Shift the scrambler data down by DATA_WIDTH
+    assign next_scrambler_data_split = {scrambler_data[DATA_WIDTH +: 128 - DATA_WIDTH]};
+
+    // If descrambling, shift in input data, else scrambler output
+    assign next_scrambler_data = DESCRAMBLE ? {idata, next_scrambler_data_split} : 
+                                              {odata, next_scrambler_data_split};
 
     // Parallel scrambler
     // Polynomial is 1 + x^39 + x^58, easier to write as inverse 1 + x^19 + x^58
@@ -44,8 +54,8 @@ module scrambler #(
     genvar gi;
     generate;
         for (gi = 0; gi < DATA_WIDTH; gi++) begin
-            assign odata[gi] = next_scrambler_data[(64-DATA_WIDTH) + 6+gi] ^ next_scrambler_data[(64-DATA_WIDTH) + 25+gi] ^ idata[gi];
+            assign odata[gi] = next_scrambler_data_split[(64-DATA_WIDTH) + 6+gi] ^ next_scrambler_data_split[(64-DATA_WIDTH) + 25+gi] ^ idata[gi];
         end
     endgenerate
 
-endmodule
+endmodule
diff --git a/src/tb/eth_10g/Makefile b/src/tb/eth_10g/Makefile
@@ -8,7 +8,6 @@ WAVES ?= 1
 VERILOG_SOURCES += $(PWD)/../../hdl/include/code_defs_pkg.svh
 VERILOG_SOURCES += $(PWD)/../../hdl/pcs/pcs.sv
 VERILOG_SOURCES += $(PWD)/../../hdl/pcs/decoder.sv
-VERILOG_SOURCES += $(PWD)/../../hdl/pcs/descrambler.sv
 VERILOG_SOURCES += $(PWD)/../../hdl/pcs/encoder.sv
 VERILOG_SOURCES += $(PWD)/../../hdl/pcs/rx_gearbox.sv
 VERILOG_SOURCES += $(PWD)/../../hdl/pcs/tx_gearbox.sv