introduce explicit etiss_rv32 and etiss_rv64 targets

tum-ei-eda · May 15, 2024 · 2a10c28 · 2a10c28
1 parent 94daccb
commit 2a10c28
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Showing 5 changed files with 42 additions and 5 deletions.
diff --git a/mlonmcu/target/_target.py b/mlonmcu/target/_target.py
@@ -21,6 +21,8 @@
     RiscvQemuTarget,
     GvsocPulpTarget,
     EtissTarget,
+    EtissRV32Target,
+    EtissRV64Target,
     AraTarget,
     AraRtlTarget,
     CV32E40PTarget,
@@ -46,6 +48,8 @@ def get_targets():
 
 register_target("etiss_pulpino", EtissPulpinoTarget)
 register_target("etiss", EtissTarget)
+register_target("etiss_rv32", EtissRV32Target)
+register_target("etiss_rv64", EtissRV64Target)
 register_target("host_x86", HostX86Target)
 register_target("corstone300", Corstone300Target)
 register_target("spike", SpikeTarget)

diff --git a/mlonmcu/target/riscv/__init__.py b/mlonmcu/target/riscv/__init__.py
@@ -1,5 +1,5 @@
 from .etiss_pulpino import EtissPulpinoTarget
-from .etiss import EtissTarget
+from .etiss import EtissTarget, EtissRV32Target, EtissRV64Target
 from .spike import SpikeTarget
 from .ovpsim import OVPSimTarget
 from .corev_ovpsim import COREVOVPSimTarget
@@ -13,6 +13,8 @@
 __all__ = [
     "EtissPulpinoTarget",
     "EtissTarget",
+    "EtissRV32Target",
+    "EtissRV64Target",
     "SpikeTarget",
     "OVPSimTarget",
     "COREVOVPSimTarget",

diff --git a/mlonmcu/target/riscv/etiss.py b/mlonmcu/target/riscv/etiss.py
@@ -171,9 +171,9 @@ def cpu_arch(self):
         if self.config.get("cpu_arch", None):
             return self.config["cpu_arch"]
         elif self.enable_pext or self.enable_vext:
-            return "RV32IMACFDPV"
+            return f"RV{self.xlen}IMACFDPV"
         else:
-            return "RV32IMACFD"
+            return f"RV{self.xlen}IMACFD"
 
     @property
     def enable_vext(self):
@@ -612,7 +612,7 @@ def get_ram_sizes(data):
         return metrics, out, artifacts
 
     def get_target_system(self):
-        return self.name
+        return "etiss"
 
     def get_platform_defs(self, platform):
         assert platform == "mlif"
@@ -649,5 +649,33 @@ def get_backend_config(self, backend, optimized_layouts=False, optimized_schedul
         return ret
 
 
+class EtissRV32Target(EtissTarget):
+    """32-bit version of etiss target"""
+
+    DEFAULTS = {
+        **EtissTarget.DEFAULTS,
+        "xlen": 32,
+        "vlen": 0,  # vectorization=off
+        "elen": 32,
+    }
+
+    def __init__(self, name="etiss_rv32", features=None, config=None):
+        super().__init__(name, features=features, config=config)
+
+
+class EtissRV64Target(EtissTarget):
+    """64-bit version of etiss target"""
+
+    DEFAULTS = {
+        **EtissTarget.DEFAULTS,
+        "xlen": 64,
+        "vlen": 0,  # vectorization=off
+        "elen": 64,
+    }
+
+    def __init__(self, name="etiss_rv64", features=None, config=None):
+        super().__init__(name, features=features, config=config)
+
+
 if __name__ == "__main__":
     cli(target=EtissTarget)
diff --git a/mlonmcu/target/riscv/etiss_pulpino.py b/mlonmcu/target/riscv/etiss_pulpino.py
@@ -53,6 +53,9 @@ def get_platform_defs(self, platform):
         ret["PULPINO_RAM_SIZE"] = self.ram_size
         return ret
 
+    def get_target_system(self):
+        return "etiss_pulpino"
+
 
 if __name__ == "__main__":
     cli(target=EtissPulpinoTarget)
diff --git a/mlonmcu/target/riscv/riscv.py b/mlonmcu/target/riscv/riscv.py
@@ -330,7 +330,7 @@ def get_platform_defs(self, platform):
         ret["RISCV_MCPU"] = self.cpu
         # llvm/clang only!
         ret["RISCV_ATTR"] = self.attr
-        ret["RISCV_LINUX"] = not self.is_bare  # TODO: add -static if linux gcc is used
+        ret["RISCV_LINUX"] = not self.is_bare
 
         def feature_helper(attrs):
             # TODO