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1. riscv-ml riscv-ml Public

   Machine Learning project using RISC-V and NVDLA on Linux

   Verilog 1 1

2. riscv-dv riscv-dv Public

   Forked from chipsalliance/riscv-dv

   SV/UVM based open-source instruction generator for RISC-V processor verification

   Python

3. ibex ibex Public

   Forked from lowRISC/ibex

   Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.

   SystemVerilog

4. lowrisc-chip lowrisc-chip Public

   Forked from lowRISC/lowrisc-chip

   The root repo for lowRISC project and FPGA demos.

   SystemVerilog

5. SCALE-Sim SCALE-Sim Public

   Forked from hoangt/SCALE-Sim

   Python

6. DNN_NeuroSim_V1.0 DNN_NeuroSim_V1.0 Public

   Forked from neurosim/DNN_NeuroSim_V1.0

   C++