Implement page table reader for aarch64

[PandaZ3D]

This PR implements part of the paging system which deals with reading the memory mappings created by the bootloader. It assumes, for now, that the hardware supports a 4 KiB translation table granule and that the bootloader uses this granule size to set up our initial page tables.

The biggest change is a slight modification of the APIs between the aarch specific code and the generic code for memory management. Specifically to determine certain properties (i.e., physical address) in a PTE for aarch64, we need to know what level we are at. For x86_64 this is a different story, and the bits in the PTE corresponding to the physical address are more/less in the same.

Summary

• code required to read the page table entries
• define the page table structure for 4 KiB pages
• cleanup code (comments, organize address, etc.)

[gvnn3]

A strange calculation, can you give the numbers names or put in a comment?

[gvnn3]

Does this need a const?

[PandaZ3D]

It can be

[gvnn3]

Thanks for the fixes.