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common/memsize.c: Fix get_ram_size() when cache is enabled #293

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Ensure that every write is flushed to memory and afterward reads are from memory.
Since the algorithm rely on the fact that accessing to not existent memory lead to write at addr / 2 without this modification accesses to aliased (not physically present) addresses are cached and wrong size is returned.

This was discovered while working on a TI AM625 based board where cache is normally enabled, see commit c02712a ("arm: mach-k3: Enable dcache in SPL").

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@eghidoli eghidoli force-pushed the check_get_mem_size branch 5 times, most recently from e753179 to 941004d Compare May 30, 2023 09:28
Build fail if CONFIG_SANDBOX_SDL is disabled due to ENOSYS undeclared.
Include errno.h before including test/lib.h.

Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
This adds dcache_status() so that code using it can build
without error on sandbox.

Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
Ensure that every write is flushed to memory and afterward reads are
from memory.
Since the algorithm rely on the fact that accessing to not existent
memory lead to write at addr / 2 without this modification accesses
to aliased (not physically present) addresses are cached and
wrong size is returned.

This was discovered while working on a TI AM625 based board
where cache is normally enabled, see commit c02712a ("arm: mach-k3: Enable dcache in SPL").

Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
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commits will be posted to mailing list. I create this MR just for CI tests

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