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memory fixes
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Utkarsh Mathur committed Apr 22, 2018
1 parent 74b47db commit 03776ef
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Showing 5 changed files with 43 additions and 30 deletions.
9 changes: 8 additions & 1 deletion tb/driver.sv
View file
Expand Up @@ -53,7 +53,13 @@ class Driver extends Agent;
// Data memory read/write handling
if( driverIf.Data_rd ) begin
driverIf.Data_dout = readDataMem(driverIf.Data_addr);
end else begin
`ifdef DEBUG_DRIVER
$display("memread : 0x%0x -> %x", driverIf.Data_addr, driverIf.Data_dout);
`endif
end else if( driverIf.Data_rd == 0 && driverIf.Data_addr !== 16'bx ) begin //&& driverIf.Data_din != 16'bx ) begin
`ifdef DEBUG_DRIVER
$display("memwrite: 0x%0x -> %x", driverIf.Data_addr, driverIf.Data_din);
`endif
writeDataMem( driverIf.Data_addr, driverIf.Data_din );
end

Expand All @@ -68,6 +74,7 @@ class Driver extends Agent;
driverIf.complete_instr = 0;
driverIf.complete_data = 0;
driverIf.Instr_dout = getInstIndex(0).encodeInst();
driverIf.Data_dout = 0;
repeat(2) @(posedge driverIf.clk);
driverIf.reset = 0;

Expand Down
14 changes: 7 additions & 7 deletions tb/interface.sv
View file
@@ -1,11 +1,11 @@
//interface Lc3_dr_if(clk, reset);
interface Lc3_dr_if(input bit clk);
logic reset;
logic complete_instr, complete_data;
logic [15:0] pc, Data_addr;
logic instrmem_rd, Data_rd;
logic [15:0] Instr_dout, Data_dout;
logic [15:0] Data_din;
reg reset;
reg complete_instr, complete_data;
reg [15:0] pc, Data_addr;
reg instrmem_rd, Data_rd;
reg [15:0] Instr_dout, Data_dout;
reg [15:0] Data_din;
endinterface

interface Lc3_mon_if( input logic clk,
Expand Down Expand Up @@ -48,7 +48,7 @@ interface Lc3_mon_if( input logic clk,
modport DECODE(output IR, E_Control, npc_out, Mem_Control, W_Control);
modport EXECUTE(output aluout, W_Control_out, Mem_Control_out, M_Data, dr, sr1, sr2, NZP, IR_Exec, pcout);
modport WB(output psr, VSR1, VSR2);
modport MEM(output Data_addr, Data_rd, Data_din, memout, input Data_dout);
modport MEM(output Data_addr, Data_rd, Data_din, memout, Data_dout);
modport CTRLR(output enable_updatePC, enable_fetch, enable_decode, enable_execute, enable_writeback,
br_taken, bypass_alu_1, bypass_alu_2, bypass_mem_1, bypass_mem_2, mem_state, Instr_dout);
endinterface
31 changes: 20 additions & 11 deletions tb/monitor.sv
View file
Expand Up @@ -87,6 +87,7 @@ class Monitor extends Agent;
reg ctrl_complete_data;
reg ctrl_complete_instr;
reg ctrl_decode_enable;
reg ctrl_enUpPC, ctrl_enFetch, ctrl_enDecode, ctrl_enExec, ctrl_enWB;

//------------------------FETCH-------------
function void fetch(); //{
Expand Down Expand Up @@ -221,11 +222,11 @@ class Monitor extends Agent;

// For ALU, short alout with pcout (not documented)
case(exec_IR[15:12])
ADD, AND, NOT: begin exec_dr = exec_IR[11:9]; exec_nzp = 3'b000; pcout = aluout; end
LDR, LDI, LEA: begin exec_dr = exec_IR[11:9]; exec_nzp = 3'b000; aluout = pcout; end
ST, STR, STI: begin exec_dr = 3'b0; exec_nzp = 3'b000; aluout = pcout; end
BR : begin exec_dr = 3'b0; exec_nzp = exec_IR[11:9]; aluout = pcout; end
JMP: begin exec_dr = 3'b0; exec_nzp = 3'b111; end
ADD, AND, NOT: begin exec_dr = exec_IR[11:9]; exec_nzp = 3'b000; pcout = aluout; end
LD, LDR, LDI, LEA: begin exec_dr = exec_IR[11:9]; exec_nzp = 3'b000; aluout = pcout; end
ST, STR, STI: begin exec_dr = 3'b0; exec_nzp = 3'b000; aluout = pcout; end
BR : begin exec_dr = 3'b0; exec_nzp = exec_IR[11:9]; aluout = pcout; end
JMP: begin exec_dr = 3'b0; exec_nzp = 3'b111; end
endcase

exec_Mdata = exec_bypass2[1] ? val_2 : exec_vsr2;
Expand Down Expand Up @@ -351,8 +352,6 @@ class Monitor extends Agent;
logic [2:0] wb_psr;
logic [15:0] wb_VSR1, wb_VSR2;

wb_W_Control = execIf.W_Control_out;

if(!monIf.reset) begin//{
case(wb_W_Control)
2'b00: regFile[wb_dr_in] = wb_aluout;
Expand Down Expand Up @@ -424,7 +423,6 @@ class Monitor extends Agent;
logic [2:0] ctrl_NZP;
logic [15:0] ctrl_ImemOut;

logic ctrl_enUpPC, ctrl_enFetch, ctrl_enDecode, ctrl_enExec, ctrl_enWB;
logic ctrl_brTaken;
logic ctrl_bpAlu1, ctrl_bpAlu2, ctrl_bpMem1, ctrl_bpMem2;
logic [3:0] ctrl_exec_opcode, ctrl_dec_opcode;
Expand Down Expand Up @@ -566,6 +564,13 @@ class Monitor extends Agent;
LD, LDR, LDI,
STI, ST, STR : begin ctrl_stallEnState_N = 2'b01; ctrl_Imem_stash = ctrl_dec_opcode; end
endcase
// FIXME: Just why?
`ifdef RUN_FIXME
if( ctrl_dec_opcode == LDI ) begin
ctrl_enFetch = 0;
ctrl_enUpPC = 0;
end
`endif
end //}
end //}

Expand Down Expand Up @@ -601,7 +606,8 @@ class Monitor extends Agent;
$display("IntermEnable: F: %0b D: %0b E: %0b W: %0b", ctrl_enFetch, ctrl_enDecode, ctrl_enExec, ctrl_enWB);
`endif

ctrl_brEnState = ctrl_brEnState_N;
// To enable mix of control and memory in the pipeline
ctrl_brEnState = |ctrl_stallEnState_N ? ctrl_brEnState : ctrl_brEnState_N;
case(ctrl_brEnState)
2'b00: begin //{
case( ctrl_ImemOut[15:12] )
Expand All @@ -625,7 +631,7 @@ class Monitor extends Agent;

`ifdef DEBUG_CTRL
$display("FinalEnable : F: %0b D: %0b E: %0b W: %0b", ctrl_enFetch, ctrl_enDecode, ctrl_enExec, ctrl_enWB);
$display("\tdrIf_complete_instr: %0b, enstate: %0b, stallState: %0b brState: %0b, Imem: %s, inst: %s, stash: %s",
$display("\tdrIf_complete_instr: %0b, enstate: %0b, stallState: %0b brState: %0b, Imem: %s, dec_inst: %s, stash: %s",
driverIf.complete_instr, ctrl_enState, ctrl_stallEnState,
ctrl_brEnState, Instruction::op2str(ctrl_ImemOut[15:12]), Instruction::op2str(ctrl_dec_opcode),
Instruction::op2str(ctrl_Imem_stash));
Expand Down Expand Up @@ -716,7 +722,7 @@ class Monitor extends Agent;
vsr1 = wbIf.VSR1;
vsr2 = wbIf.VSR2;
// Sensitize on all DUT async signals
@(execIf.sr1 or execIf.sr2 or memIf.memout or wbIf.VSR1 or wbIf.VSR2);
@(execIf.sr1 or execIf.sr2 or memIf.memout or wbIf.VSR1 or wbIf.VSR2 or driverIf.instrmem_rd);

if( !monIf.reset ) begin
//--------------------- EXEC ---------------------
Expand All @@ -738,6 +744,9 @@ class Monitor extends Agent;
endcase

check("A_EXEC", WARN, exec_sr2 === sr2, $psprintf("sr2 unmatched! (%0x != %0x)", exec_sr2, sr2));
// FIXME
//check("A_EXEC", WARN, ctrl_enFetch === driverIf.instrmem_rd, $psprintf("instrmem_rd unmatched! (%0x != %0x)",
// ctrl_enFetch, driverIf.instrmem_rd));

//--------------------- MEM ---------------------
check("A_MEM", WARN, mem_Dout === memout, $psprintf("memout unmatched! (%0x != %0x)", mem_Dout, memout));
Expand Down
2 changes: 1 addition & 1 deletion tb/tests.sv
View file
Expand Up @@ -11,7 +11,7 @@ class BaseStoreLoadTest extends Test;
// Populates env's instruct mem
virtual function void sequenceInstr();
//integer numTrans = 8 + 100 + 100; // R0-7 + warmup + test
integer numTrans = 100*9 + 100;
integer numTrans = 100*9 + 200;
integer ctrl = 0, mem = 0;
integer instCnt = 0;
Instruction instMemEntry = new;
Expand Down
17 changes: 7 additions & 10 deletions tb/top.sv
View file
Expand Up @@ -2,15 +2,16 @@
`define STALL_THRESH 1000
`define BASE_ADDR 16'h3000
`define DYN_INST_CNT 100000
`define LC3_PIPE_DEPTH 5
`define LC3_PIPE_DEPTH 6
//`define DEBUG_DRIVER
//`define DEBUG_EXEC
//`define DEBUG_FETCH
`define DEBUG_WB
//`define DEBUG_CTRL
//`define DEBUG_WB
`define DEBUG_CTRL
`define T_FETCH_MAX 0
`define T_DATA_MAX 0
//`define TOP_MONITOR
`define RUN_FIXME

`include "types.sv"
`include "interface.sv"
Expand All @@ -30,10 +31,6 @@ module top();

reg clk = 0;

wire Data_rd;
wire [15:0] Data_addr;
wire [15:0] Data_din;

// Clock generation
always #5 clk = ~clk;

Expand Down Expand Up @@ -73,10 +70,10 @@ LC3 dut( .clock(lc3if.clk),
.pc(lc3if.pc),
.instrmem_rd(lc3if.instrmem_rd),
.Instr_dout(lc3if.Instr_dout),
.Data_addr(Data_addr),
.Data_addr(lc3if.Data_addr),
.complete_instr(lc3if.complete_instr),
.complete_data(lc3if.complete_data),
.Data_din(Data_din),
.Data_din(lc3if.Data_din),
.Data_dout(lc3if.Data_dout),
.Data_rd(Data_rd) );
.Data_rd(lc3if.Data_rd) );
endmodule

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