Add Wishbone protocol support

[manili]

Hi,

I would like to add Wishbone protocol support to Constellation. However, the documentation is confusing me. Furthermore, due to the changes made to Chipyard (refer to #41), it is challenging to follow the documentation and understand what is happening under the hood. Do you have any suggestions on how I can get started with this process?

[jerryz123]

Hi Mohammad, adding Wishbone support would be a great feature. I apologize for the sparseness of the documentation.

The way TileLink and AXI4 are implemented is more complex than what minimal Wishbone support would require, as they take advantage of features in Diplomacy.

The way this is designed, all you really need to implement is an instance of ProtocolParams, which describes how some higher-level protocol can be packetized, how to convert protocol messages to destination IDs, and relationships between protocol channels. In this PR (https://github.com/ucb-bar/chipyard/pull/1380/files): I show how a simple single channel protocol can be lowered to Constellation by constructing a specific ProtocolParams.

I admit the documentation around ProtocolParams is lacking. Please let me know what specifically you are confused by, and I can write something up and add it to the documentation.

[manili]

Hi Jerry,
Thanks a lot for the reply. I greatly appreciate it. I tried to figure things out by reading the PR but still it seems confusing to me. I think I have to become more familiar with the code and understand "underlying concepts". Of course the most important cause of the confusion is that I never had the chance to implement a NoC by myself and all I know about it is the theoretical aspects. I hope to be able to help document the process in detail after the project is implemented, so that others can benefit from the power of Constellation.

Let's talk about the scenario and why I need Constellation. I'm going to design a Many-core RISC-V chip using ASAP7 predictive PDK and OpenROAD/ORFS PnR toolset in a ~10mm^2 area. My chip shall include the following:

1. Thousand modified version of Subservient SoC. These cores do not have any interfaces except the SRAM interface which uses simple Wishbone protocol.
2. Four 8KB SRAM memories which again uses Wishbone protocol to connect to the outside world.
3. One full version of Subservient SoC that will Manage/Schedule the whole fabric. It will read the input from DRAM/GPIO, program SRAMs, initialize the Subservient cores and start the processing. After process has been done by the cores, it will collect the data and send it back to the DRAM/GPIO.
4. 2D-mesh topology NoC that will be generated by the Constellation and will connect all the cores and memories together.

Now, please let me understand better the process and Constellation internals by asking a very naive question:
AFAIK in a 2D-mesh topology of NoC every core must connect to the an adjacent router. Is it a good idea to memory-map all cores and SRAMs to some addresses and create sort of LUT at router to convert the address to the unique Id of the core?