Pinned repositories

  1. chisel-tutorial

    chisel tutorial exercises and answers

    Scala 159 83

  2. chisel-template

    A template project for beginning new Chisel work

    Scala 42 18

  • Berkeley Out-of-Order Machine

    Scala 239 69 Updated Aug 14, 2018
  • Scala 5 10 Updated Aug 14, 2018
  • HAMMER: Highly Agile Masks Made Effortlessly from RTL

    Python 22 5 BSD-3-Clause Updated Aug 13, 2018
  • A prototype GUI for chisel-development

    Scala 1 Updated Aug 8, 2018
  • Simple RISC-V 3-stage Pipeline in Chisel

    Scala 45 8 BSD-3-Clause Updated Aug 8, 2018
  • FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL

    Scala 3 BSD-3-Clause Updated Aug 8, 2018
  • Mirror of Chisel3 Github wiki https://github.com/ucb-bar/chisel3/wiki

    5 6 Updated Aug 3, 2018
  • Support for Rocket Chip on Zynq FPGAs

    Tcl 155 86 Updated Jul 29, 2018
  • SoftFloat release 3

    C 37 31 Updated Jul 26, 2018
  • A Library of Chisel3 Tools for Digital Signal Processing

    Scala 22 5 BSD-3-Clause Updated Jul 25, 2018
  • RISC-V Torture Test

    Scala 19 10 Updated Jul 19, 2018
  • prebuilt images for zedboard zynq fpga

    4 6 Updated Jul 8, 2018
  • Generator Bootcamp Material: Learn Chisel the Right Way

    Jupyter Notebook 39 14 BSD-3-Clause Updated Jul 6, 2018
  • yosys

    Forked from YosysHQ/yosys

    Yosys Open SYnthesis Suite

    C++ 172 ISC Updated Jun 29, 2018
  • Useful utilities for BAR projects

    Scala 3 BSD-3-Clause Updated Jun 25, 2018
  • Simple MIDAS Examples

    Scala 4 BSD-3-Clause Updated Jun 23, 2018
  • A template project for beginning new Chisel work

    Scala 42 18 Updated Jun 23, 2018
  • Scala 2 Updated Jun 4, 2018
  • chisel tutorial exercises and answers

    Scala 159 83 Updated May 30, 2018
  • Scala 42 23 Updated May 16, 2018
  • C 35 36 Updated May 15, 2018
  • educational microarchitectures for risc-v isa

    Scala 204 65 Updated May 8, 2018
  • 1 4 Updated Apr 18, 2018
  • 2 1 Updated Apr 18, 2018
  • Scala 403 111 Updated Apr 18, 2018
  • Memory System Microbenchmarks

    C 18 7 Updated Feb 13, 2018
  • TestFloat release 3

    C 10 3 Updated Jan 27, 2018
  • A zynq host-platform shell for midas generated simulators.

    Tcl 2 Updated Dec 19, 2017
  • MIDAS RocketChip Template

    Scala 4 1 BSD-3-Clause Updated Dec 15, 2017
  • UCB-BAR fork of LLVM! NOT UPSTREAM RISCV LLVM

    C++ 76 48 Updated Dec 14, 2017