An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
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An open framework for designing and deploying custom AI-driven HW/SW co-design flows fast
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Berkeley's Spatial Array Generator
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Hammer: Highly Agile Masks Made Effortlessly from RTL
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A Heterogeneous GPU Platform for AI and Neural Graphics
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Chisel RISC-V Vector 1.0 Implementation
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MLIR dialect for Atlas.
MLIR-in as a compiler stack for ucb-bar
MX Gemmini software contract, TorchAO adapter, and MLIR handoff
Gemmini extensions for Spike
Any model in Torch or JAX format to MLIR frontend dialects.
An open-source UCIe implementation
Configurable low-precision floating-point and microscaling hardware in Chisel
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