mips guest needs CP0 register support

[lunixbochs]

http://en.wikichip.org/wiki/mips/coprocessor_0

For example we need access to CP0_UserLocal to set thread-local storage.

Edit: I thought I was going to work around this by running shellcode, but it's in the middle of a syscall so I need to trampoline and I haven't implemented that yet, so this is actually blocking Usercorn mips Linux support.

[aquynh]

yes pull request, please.

[lunixbochs]

actually according to this, the instruction rdhwr $v1, $29 to read the current TLS address seems to trap: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=28126#c3

so instead we might just need an instruction hook for it

I tried running mtc0 manually but we don't have the feature flag CP0C3_ULRI, which means we just need a hook for rdhwr that works like the x86 IN helpers.