Updated lwIP source code and Xilinx port. Patches are related to Free…

…RTOS operation.

See: Xilinx/embeddedsw@aafd211#diff-368bdee3886a0aaa5a90f32e9aba6aac

Vivado/ipmc_zynq_vivado.sdk/common/lwIP/src/contrib/ports/xilinx/include/netif/xadapter.h

@@ -58,6 +58,9 @@ struct xemac_s {
 #if !NO_SYS
     sys_sem_t sem_rx_data_available;
 #endif
+#if defined(OS_IS_FREERTOS) && defined(__arm__) && !defined(ARMR5)
+	TimerHandle_t xTimer;
+#endif
 };
 
 void 		lwip_raw_init();

Vivado/ipmc_zynq_vivado.sdk/common/lwIP/src/contrib/ports/xilinx/netif/xadapter.c

@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2007 - 2014 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2007 - 2017 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -135,7 +135,7 @@ xemac_add(struct netif *netif,
 			case xemac_type_xps_emaclite:
 #ifdef XLWIP_CONFIG_INCLUDE_EMACLITE
 				return netif_add(netif, ipaddr, netmask, gw,
-					(void*)mac_baseaddr,
+					(void*)(UINTPTR)mac_baseaddr,
 					xemacliteif_init,
 #if NO_SYS
 					ethernet_input
@@ -149,7 +149,7 @@ xemac_add(struct netif *netif,
 			case xemac_type_axi_ethernet:
 #ifdef XLWIP_CONFIG_INCLUDE_AXI_ETHERNET
 				return netif_add(netif, ipaddr, netmask, gw,
-					(void*)mac_baseaddr,
+					(void*)(UINTPTR)mac_baseaddr,
 					xaxiemacif_init,
 #if NO_SYS
 					ethernet_input

Vivado/ipmc_zynq_vivado.sdk/common/lwIP/src/contrib/ports/xilinx/netif/xemacpsif.c

@@ -86,6 +86,11 @@ static u8_t xemacps_mcast_entry_mask = 0;
 XEmacPs_Config *mac_config;
 struct netif *NetIf;
 
+#if defined(OS_IS_FREERTOS) && defined(__arm__) && !defined(ARMR5)
+int32_t lExpireCounter = 0;
+#define RESETRXTIMEOUT 10
+#endif
+
 /*
  * this function is always called with interrupts off
  * this function also assumes that there are available BD's
@@ -266,6 +271,21 @@ s32_t xemacpsif_input(struct netif *netif)
 }
 
 
+#if defined(OS_IS_FREERTOS) && defined(__arm__) && !defined(ARMR5)
+void vTimerCallback( TimerHandle_t pxTimer )
+{
+	/* Do something if the pxTimer parameter is NULL */
+	configASSERT(pxTimer);
+
+	lExpireCounter++;
+	/* If the timer has expired 100 times then reset RX */
+	if(lExpireCounter >= RESETRXTIMEOUT) {
+		lExpireCounter = 0;
+		xemacpsif_resetrx_on_no_rxdata(NetIf);
+	}
+}
+ #endif
+
 static err_t low_level_init(struct netif *netif)
 {
 	UINTPTR mac_address = (UINTPTR)(netif->state);
@@ -337,6 +357,17 @@ static err_t low_level_init(struct netif *netif)
 	XEmacPs_WriteReg(xemacpsif->emacps.Config.BaseAddress,
 											XEMACPS_DMACR_OFFSET, dmacrreg);
 
+#if defined(OS_IS_FREERTOS) && defined(__arm__) && !defined(ARMR5)
+	/* Freertos tick is 10ms by default; set period to the same */
+	xemac->xTimer = xTimerCreate("Timer", 10, pdTRUE, ( void * ) 1, vTimerCallback);
+	if (xemac->xTimer == NULL) {
+		ipmc_lwip_printf("In %s:Timer creation failed....\r\n", __func__);
+	} else {
+		if(xTimerStart(xemac->xTimer, 0) != pdPASS) {
+			ipmc_lwip_printf("In %s:Timer start failed....\r\n", __func__);
+		}
+	}
+#endif
 	setup_isr(xemac);
 	init_dma(xemac);
 	start_emacps(xemacpsif);

Vivado/ipmc_zynq_vivado.sdk/common/lwIP/src/contrib/ports/xilinx/netif/xemacpsif_dma.c

@@ -311,7 +311,11 @@ XStatus emacps_sgsend(xemacpsif_s *xemacpsif, struct pbuf *p)
 		/* Send the data from the pbuf to the interface, one pbuf at a
 		   time. The size of the data in each pbuf is kept in the ->len
 		   variable. */
-		Xil_DCacheFlushRange((UINTPTR)q->payload, (UINTPTR)q->len);
+		// TODO: For when Vivado gets update to 2017.4
+		//if (xemacpsif->emacps.Config.IsCacheCoherent == 0) {
+			Xil_DCacheFlushRange((UINTPTR)q->payload, (UINTPTR)q->len);
+		//}
+
 		XEmacPs_BdSetAddressTx(txbd, (UINTPTR)q->payload);
 
 #ifdef ZYNQMP_USE_JUMBO
@@ -413,9 +417,14 @@ void setup_rx_bds(xemacpsif_s *xemacpsif, XEmacPs_BdRing *rxring)
 			return;
 		}
 #ifdef ZYNQMP_USE_JUMBO
-		Xil_DCacheInvalidateRange((UINTPTR)p->payload, (UINTPTR)MAX_FRAME_SIZE_JUMBO);
+		if (xemacpsif->emacps.Config.IsCacheCoherent == 0) {
+			Xil_DCacheInvalidateRange((UINTPTR)p->payload, (UINTPTR)MAX_FRAME_SIZE_JUMBO);
+		}
 #else
-		Xil_DCacheInvalidateRange((UINTPTR)p->payload, (UINTPTR)XEMACPS_MAX_FRAME_SIZE);
+		// TODO: For when Vivado gets update to 2017.4
+		//if (xemacpsif->emacps.Config.IsCacheCoherent == 0) {
+			Xil_DCacheInvalidateRange((UINTPTR)p->payload, (UINTPTR)XEMACPS_MAX_FRAME_SIZE);
+		//}
 #endif
 		bdindex = XEMACPS_BD_TO_INDEX(rxring, rxbd);
 		temp = (u32 *)rxbd;
@@ -551,6 +560,24 @@ XStatus init_dma(struct xemac_s *xemac)
 	XEmacPs_Bd *bdrxterminate;
 	u32 *temp;
 
+	/*
+	 * Disable L1 prefetch if the processor type is Cortex A53. It is
+	 * observed that the L1 prefetching for ARMv8 can cause issues while
+     * dealing with cache memory on Rx path. On Rx path, the lwIP adapter
+	 * does a clean and invalidation of buffers (pbuf payload) before
+     * allocating them to Rx BDs. However, there are chances that the
+	 * the same cache line may get prefetched by the time Rx data is
+     * DMAed to the same buffer. In such cases, CPU fetches stale data from
+     * cache memory instead of getting them from memory. To avoid such
+     * scenarios L1 prefetch is being disabled for ARMv8. That can cause
+	 * a performance degaradation in the range of 3-5%. In tests, it is
+	 * generally observed that this performance degaradation is quite
+	 * insignificant to be really visible.
+	 */
+#if defined __aarch64__
+	Xil_ConfigureL1Prefetch(0);
+#endif
+
 	xemacpsif_s *xemacpsif = (xemacpsif_s *)(xemac->state);
 	struct xtopology_t *xtopologyp = &xtopology[xemac->topology_index];
 
@@ -694,9 +721,14 @@ XStatus init_dma(struct xemac_s *xemac)
 		*temp = 0;
 		dsb();
 #ifdef ZYNQMP_USE_JUMBO
-		Xil_DCacheInvalidateRange((UINTPTR)p->payload, (UINTPTR)MAX_FRAME_SIZE_JUMBO);
+		if (xemacpsif->emacps.Config.IsCacheCoherent == 0) {
+			Xil_DCacheInvalidateRange((UINTPTR)p->payload, (UINTPTR)MAX_FRAME_SIZE_JUMBO);
+		}
 #else
-		Xil_DCacheInvalidateRange((UINTPTR)p->payload, (UINTPTR)XEMACPS_MAX_FRAME_SIZE);
+		// TODO: For when Vivado gets update to 2017.4
+		//if (xemacpsif->emacps.Config.IsCacheCoherent == 0) {
+			Xil_DCacheInvalidateRange((UINTPTR)p->payload, (UINTPTR)XEMACPS_MAX_FRAME_SIZE);
+		//}
 #endif
 		XEmacPs_BdSetAddressRx(rxbd, (UINTPTR)p->payload);
 
@@ -724,10 +756,10 @@ XStatus init_dma(struct xemac_s *xemac)
 		XEmacPs_Out32((xemacpsif->emacps.Config.BaseAddress + XEMACPS_RXQ1BASE_OFFSET),
 				   (UINTPTR)bdrxterminate);
 		XEmacPs_BdClear(bdtxterminate);
-		XEmacPs_BdSetStatus(bdrxterminate, (XEMACPS_TXBUF_USED_MASK |
+		XEmacPs_BdSetStatus(bdtxterminate, (XEMACPS_TXBUF_USED_MASK |
 						XEMACPS_TXBUF_WRAP_MASK));
 		XEmacPs_Out32((xemacpsif->emacps.Config.BaseAddress + XEMACPS_TXQBASE_OFFSET),
-				   (UINTPTR)bdrxterminate);
+				   (UINTPTR)bdtxterminate);
 	}
 
 

Vivado/ipmc_zynq_vivado.sdk/common/lwIP/src/contrib/ports/xilinx/netif/xemacpsif_hw.c

@@ -209,7 +209,7 @@ void emacps_error_handler(void *arg,u8 Direction, u32 ErrorWord)
 	xemac = (struct xemac_s *)(arg);
 	xemacpsif = (xemacpsif_s *)(xemac->state);
 	rxring = &XEmacPs_GetRxRing(&xemacpsif->emacps);
-	txring = &XEmacPs_GetRxRing(&xemacpsif->emacps);
+	txring = &XEmacPs_GetTxRing(&xemacpsif->emacps);
 
 	if (ErrorWord != 0) {
 		switch (Direction) {

Vivado/ipmc_zynq_vivado.sdk/common/lwIP/src/contrib/ports/xilinx/netif/xemacpsif_physpeed.c

@@ -111,6 +111,11 @@
 #include "xparameters_ps.h"
 #include "xparameters.h"
 
+#if defined (__aarch64__)
+#include "bspconfig.h"
+#include "xil_smc.h"
+#endif
+
 /* Advertisement control register. */
 #define ADVERTISE_10HALF		0x0020  /* Try for 10mbps half-duplex  */
 #define ADVERTISE_10FULL		0x0040  /* Try for 10mbps full-duplex  */
@@ -904,12 +909,28 @@ static void SetUpSLCRDivisors(u32_t mac_baseaddr, s32_t speed)
 		}
 
 		if (CrlApbDiv0 != 0 && CrlApbDiv1 != 0) {
+		#if EL1_NONSECURE
+			XSmc_OutVar RegRead;
+			RegRead = Xil_Smc(MMIO_READ_SMC_FID, (u64)(CrlApbBaseAddr),
+								0, 0, 0, 0, 0, 0);
+			CrlApbGemCtrl = RegRead.Arg0 >> 32;
+		#else
 			CrlApbGemCtrl = *(volatile u32_t *)(UINTPTR)(CrlApbBaseAddr);
+        #endif
 			CrlApbGemCtrl &= ~CRL_APB_GEM_DIV0_MASK;
 			CrlApbGemCtrl |= CrlApbDiv0 << CRL_APB_GEM_DIV0_SHIFT;
 			CrlApbGemCtrl &= ~CRL_APB_GEM_DIV1_MASK;
 			CrlApbGemCtrl |= CrlApbDiv1 << CRL_APB_GEM_DIV1_SHIFT;
+		#if EL1_NONSECURE
+			Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(CrlApbBaseAddr) | ((u64)(0xFFFFFFFF) << 32),
+				(u64)CrlApbGemCtrl, 0, 0, 0, 0, 0);
+			do {
+			RegRead = Xil_Smc(MMIO_READ_SMC_FID, (u64)(CrlApbBaseAddr),
+				0, 0, 0, 0, 0, 0);
+			} while((RegRead.Arg0 >> 32) != CrlApbGemCtrl);
+		#else
 			*(volatile u32_t *)(UINTPTR)(CrlApbBaseAddr) = CrlApbGemCtrl;
+        #endif
 		} else {
 			ipmc_lwip_printf("Clock Divisors incorrect - Please check\r\n");
 		}

Vivado/ipmc_zynq_vivado.sdk/common/lwIP/src/contrib/ports/xilinx/sys_arch.c

@@ -6,7 +6,7 @@
 
 /******************************************************************************
 *
-* Copyright (C) 2007 - 2014 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2007 - 2017 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -476,7 +476,7 @@ void sys_sem_set_invalid(sys_sem_t *sem)
 /* Very crude mechanism used to determine if the critical section handling
 functions are being called from an interrupt context or not.  This relies on
 the interrupt handler setting this variable manually. */
-extern long xInsideISR;
+extern u32 xInsideISR;
 
 /*---------------------------------------------------------------------------*
  * Routine:  sys_mbox_new
@@ -764,6 +764,7 @@ portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
  *---------------------------------------------------------------------------*/
 err_t sys_sem_new( sys_sem_t *pxSemaphore, u8_t ucCount )
 {
+	(void) ucCount;
 err_t xReturn = ERR_MEM;
 
 	*pxSemaphore = xSemaphoreCreateBinary();
@@ -1006,7 +1007,7 @@ xTaskHandle xCreatedTask;
 portBASE_TYPE xResult;
 sys_thread_t xReturn;
 
-	xResult = xTaskCreate( pxThread, ( char * ) pcName, iStackSize, pvArg, iPriority, &xCreatedTask );
+	xResult = xTaskCreate( pxThread, ( const char * const) pcName, iStackSize, pvArg, iPriority, &xCreatedTask );
 
 	if( xResult == pdPASS )
 	{

Vivado/ipmc_zynq_vivado.sdk/common/lwIP/src/lwip-1.4.1/src/include/ipv4/lwip/ip_addr.h

@@ -210,7 +210,7 @@ u8_t ip4_addr_netmask_valid(u32_t netmask);
 #define ip_addr_islinklocal(addr1) (((addr1)->addr & PP_HTONL(0xffff0000UL)) == PP_HTONL(0xa9fe0000UL))
 
 #define ip_addr_debug_print(debug, ipaddr) \
-  LWIP_DEBUGF(debug, ("%" U16_F ".%" U16_F ".%" U16_F ".%" U16_F,             \
+  LWIP_DEBUGF(debug, ("%"U16_F".%"U16_F".%"U16_F".%"U16_F,             \
                       ipaddr != NULL ? ip4_addr1_16(ipaddr) : 0,       \
                       ipaddr != NULL ? ip4_addr2_16(ipaddr) : 0,       \
                       ipaddr != NULL ? ip4_addr3_16(ipaddr) : 0,       \