Build XML uHAL memory map for oRSC FE

[ekfriis]

We need to make the corresponding memory map XML to the CTP example [1] for the oRSC. Here is the relevant oRSC FE HDL from Matthias:

 when x"10008000" => fpled1grnena_b_reg  <= BRAM_WRDATA_A(0)   ;

means that a register that drives the LED green is at address 0x10008000.

        when x"10008000" => fpled1grnena_b_reg  <= BRAM_WRDATA_A(0)   ;
        when x"10008004" => fpled1redena_b_reg  <= BRAM_WRDATA_A(0)   ;
        when x"10008008" => fpled2grnena_b_reg  <= BRAM_WRDATA_A(0)   ;
        when x"1000800C" => fpled2redena_b_reg  <= BRAM_WRDATA_A(0)   ;
        when x"10008010" => fpled3grnena_b_reg  <= BRAM_WRDATA_A(0)   ;
        when x"10008014" => fpled3redena_b_reg  <= BRAM_WRDATA_A(0)   ;
        when x"10008018" => s6yellowled_reg     <= BRAM_WRDATA_A(0)   ;
        when x"1000801C" => s6orangeled_reg     <= BRAM_WRDATA_A(0)   ;
        when x"10008020" => s6greenled_reg      <= BRAM_WRDATA_A(0)   ;
        when x"10008024" => lvshftregdata_reg   <= BRAM_WRDATA_A(0)   ;
        when x"10008028" => lvmuxregclk_reg     <= BRAM_WRDATA_A(0)   ;
        when x"1000802C" => lvdelayregclk_reg   <= BRAM_WRDATA_A(0)   ;
        when x"10008030" => lvshftregrst_reg    <= BRAM_WRDATA_A(0)   ;
        when x"10008034" => lv2eclspare1_reg    <= BRAM_WRDATA_A(0)   ;
        when x"10008038" => lv2eclspare2_reg    <= BRAM_WRDATA_A(0)   ;
        when x"1000803C" => lvwstb_b_reg        <= BRAM_WRDATA_A(7 downto 0) ;
        when x"10008040" => avagorst_b_reg      <= BRAM_WRDATA_A(0)   ;
        when x"10008044" => ckarst_reg          <= BRAM_WRDATA_A(0)   ;
        when x"10008048" => ckcrst_reg          <= BRAM_WRDATA_A(0)   ;
        when x"1000804C" => k7_program_b_reg    <= BRAM_WRDATA_A(0)   ;

[1] https://svnweb.cern.ch/trac/cactus/browser/trunk/cactuscore/softipbus/etc/ctp6_fe.xml