[wasm-simd] Remove F32x4RecipApprox and F32x4RecipSqrtApprox

These were originally proposed as a part of the fixed-width SIMD proposal, and were then migrated to the relaxed-simd proposal which also deems these operations out of scope. Github issue: WebAssembly/relaxed-simd#4 Bug: v8:12284 Change-Id: I65ceb6dfd25c43cf49bd7ec5b5ecd6b32cc3516a Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3595970 Reviewed-by: Thibaud Michaud <thibaudm@chromium.org> Commit-Queue: Deepti Gandluri <gdeepti@chromium.org> Cr-Commit-Position: refs/heads/main@{#80125}
v8 · Apr 22, 2022 · b081948 · b081948
1 parent 88ead17
commit b081948
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Showing 48 changed files with 1 addition and 178 deletions.
diff --git a/src/compiler/backend/arm/code-generator-arm.cc b/src/compiler/backend/arm/code-generator-arm.cc
@@ -2206,14 +2206,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
 #undef S_FROM_Q
       break;
     }
-    case kArmF32x4RecipApprox: {
-      __ vrecpe(i.OutputSimd128Register(), i.InputSimd128Register(0));
-      break;
-    }
-    case kArmF32x4RecipSqrtApprox: {
-      __ vrsqrte(i.OutputSimd128Register(), i.InputSimd128Register(0));
-      break;
-    }
     case kArmF32x4Add: {
       __ vadd(i.OutputSimd128Register(), i.InputSimd128Register(0),
               i.InputSimd128Register(1));

diff --git a/src/compiler/backend/arm/instruction-codes-arm.h b/src/compiler/backend/arm/instruction-codes-arm.h
@@ -167,8 +167,6 @@ namespace compiler {
   V(ArmF32x4Abs)                   \
   V(ArmF32x4Neg)                   \
   V(ArmF32x4Sqrt)                  \
-  V(ArmF32x4RecipApprox)           \
-  V(ArmF32x4RecipSqrtApprox)       \
   V(ArmF32x4Add)                   \
   V(ArmF32x4Sub)                   \
   V(ArmF32x4Mul)                   \

diff --git a/src/compiler/backend/arm/instruction-scheduler-arm.cc b/src/compiler/backend/arm/instruction-scheduler-arm.cc
@@ -146,8 +146,6 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kArmF32x4Abs:
     case kArmF32x4Neg:
     case kArmF32x4Sqrt:
-    case kArmF32x4RecipApprox:
-    case kArmF32x4RecipSqrtApprox:
     case kArmF32x4Add:
     case kArmF32x4Sub:
     case kArmF32x4Mul:

diff --git a/src/compiler/backend/arm/instruction-selector-arm.cc b/src/compiler/backend/arm/instruction-selector-arm.cc
@@ -2585,8 +2585,6 @@ void InstructionSelector::VisitWord32AtomicPairCompareExchange(Node* node) {
   V(F32x4UConvertI32x4, kArmF32x4UConvertI32x4)         \
   V(F32x4Abs, kArmF32x4Abs)                             \
   V(F32x4Neg, kArmF32x4Neg)                             \
-  V(F32x4RecipApprox, kArmF32x4RecipApprox)             \
-  V(F32x4RecipSqrtApprox, kArmF32x4RecipSqrtApprox)     \
   V(I64x2Abs, kArmI64x2Abs)                             \
   V(I64x2SConvertI32x4Low, kArmI64x2SConvertI32x4Low)   \
   V(I64x2SConvertI32x4High, kArmI64x2SConvertI32x4High) \

diff --git a/src/compiler/backend/arm64/code-generator-arm64.cc b/src/compiler/backend/arm64/code-generator-arm64.cc
@@ -2298,8 +2298,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
     }
       SIMD_UNOP_CASE(kArm64F32x4SConvertI32x4, Scvtf, 4S);
       SIMD_UNOP_CASE(kArm64F32x4UConvertI32x4, Ucvtf, 4S);
-      SIMD_UNOP_CASE(kArm64F32x4RecipApprox, Frecpe, 4S);
-      SIMD_UNOP_CASE(kArm64F32x4RecipSqrtApprox, Frsqrte, 4S);
     case kArm64FMulElement: {
       VectorFormat s_f =
           ScalarFormatFromLaneSize(LaneSizeField::decode(opcode));

diff --git a/src/compiler/backend/arm64/instruction-codes-arm64.h b/src/compiler/backend/arm64/instruction-codes-arm64.h
@@ -237,8 +237,6 @@ namespace compiler {
   V(Arm64F64x2PromoteLowF32x4)                       \
   V(Arm64F32x4SConvertI32x4)                         \
   V(Arm64F32x4UConvertI32x4)                         \
-  V(Arm64F32x4RecipApprox)                           \
-  V(Arm64F32x4RecipSqrtApprox)                       \
   V(Arm64F32x4Qfma)                                  \
   V(Arm64F32x4Qfms)                                  \
   V(Arm64F32x4Pmin)                                  \

diff --git a/src/compiler/backend/arm64/instruction-scheduler-arm64.cc b/src/compiler/backend/arm64/instruction-scheduler-arm64.cc
@@ -181,8 +181,6 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kArm64F64x2PromoteLowF32x4:
     case kArm64F32x4SConvertI32x4:
     case kArm64F32x4UConvertI32x4:
-    case kArm64F32x4RecipApprox:
-    case kArm64F32x4RecipSqrtApprox:
     case kArm64F32x4Qfma:
     case kArm64F32x4Qfms:
     case kArm64F32x4Pmin:

diff --git a/src/compiler/backend/arm64/instruction-selector-arm64.cc b/src/compiler/backend/arm64/instruction-selector-arm64.cc
@@ -3477,8 +3477,6 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
   V(F64x2PromoteLowF32x4, kArm64F64x2PromoteLowF32x4)           \
   V(F32x4SConvertI32x4, kArm64F32x4SConvertI32x4)               \
   V(F32x4UConvertI32x4, kArm64F32x4UConvertI32x4)               \
-  V(F32x4RecipApprox, kArm64F32x4RecipApprox)                   \
-  V(F32x4RecipSqrtApprox, kArm64F32x4RecipSqrtApprox)           \
   V(F32x4DemoteF64x2Zero, kArm64F32x4DemoteF64x2Zero)           \
   V(I64x2BitMask, kArm64I64x2BitMask)                           \
   V(I32x4SConvertF32x4, kArm64I32x4SConvertF32x4)               \

diff --git a/src/compiler/backend/ia32/code-generator-ia32.cc b/src/compiler/backend/ia32/code-generator-ia32.cc
@@ -2138,14 +2138,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       __ Sqrtps(i.OutputSimd128Register(), i.InputSimd128Register(0));
       break;
     }
-    case kIA32F32x4RecipApprox: {
-      __ Rcpps(i.OutputSimd128Register(), i.InputOperand(0));
-      break;
-    }
-    case kIA32F32x4RecipSqrtApprox: {
-      __ Rsqrtps(i.OutputSimd128Register(), i.InputOperand(0));
-      break;
-    }
     case kIA32F32x4Add: {
       __ Addps(i.OutputSimd128Register(), i.InputSimd128Register(0),
                i.InputOperand(1));

diff --git a/src/compiler/backend/ia32/instruction-codes-ia32.h b/src/compiler/backend/ia32/instruction-codes-ia32.h
@@ -161,8 +161,6 @@ namespace compiler {
   V(IA32F32x4SConvertI32x4)        \
   V(IA32F32x4UConvertI32x4)        \
   V(IA32F32x4Sqrt)                 \
-  V(IA32F32x4RecipApprox)          \
-  V(IA32F32x4RecipSqrtApprox)      \
   V(IA32F32x4Add)                  \
   V(IA32F32x4Sub)                  \
   V(IA32F32x4Mul)                  \

diff --git a/src/compiler/backend/ia32/instruction-scheduler-ia32.cc b/src/compiler/backend/ia32/instruction-scheduler-ia32.cc
@@ -145,8 +145,6 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kIA32F32x4SConvertI32x4:
     case kIA32F32x4UConvertI32x4:
     case kIA32F32x4Sqrt:
-    case kIA32F32x4RecipApprox:
-    case kIA32F32x4RecipSqrtApprox:
     case kIA32F32x4Add:
     case kIA32F32x4Sub:
     case kIA32F32x4Mul:

diff --git a/src/compiler/backend/ia32/instruction-selector-ia32.cc b/src/compiler/backend/ia32/instruction-selector-ia32.cc
@@ -2371,8 +2371,6 @@ void InstructionSelector::VisitWord32AtomicPairCompareExchange(Node* node) {
   V(F32x4DemoteF64x2Zero)   \
   V(F32x4Sqrt)              \
   V(F32x4SConvertI32x4)     \
-  V(F32x4RecipApprox)       \
-  V(F32x4RecipSqrtApprox)   \
   V(I64x2BitMask)           \
   V(I64x2SConvertI32x4Low)  \
   V(I64x2SConvertI32x4High) \

diff --git a/src/compiler/backend/instruction-selector.cc b/src/compiler/backend/instruction-selector.cc
@@ -2013,10 +2013,6 @@ void InstructionSelector::VisitNode(Node* node) {
       return MarkAsSimd128(node), VisitF32x4Neg(node);
     case IrOpcode::kF32x4Sqrt:
       return MarkAsSimd128(node), VisitF32x4Sqrt(node);
-    case IrOpcode::kF32x4RecipApprox:
-      return MarkAsSimd128(node), VisitF32x4RecipApprox(node);
-    case IrOpcode::kF32x4RecipSqrtApprox:
-      return MarkAsSimd128(node), VisitF32x4RecipSqrtApprox(node);
     case IrOpcode::kF32x4Add:
       return MarkAsSimd128(node), VisitF32x4Add(node);
     case IrOpcode::kF32x4Sub:

diff --git a/src/compiler/backend/loong64/instruction-codes-loong64.h b/src/compiler/backend/loong64/instruction-codes-loong64.h
@@ -212,8 +212,6 @@ namespace compiler {
   V(Loong64F32x4Abs)                   \
   V(Loong64F32x4Neg)                   \
   V(Loong64F32x4Sqrt)                  \
-  V(Loong64F32x4RecipApprox)           \
-  V(Loong64F32x4RecipSqrtApprox)       \
   V(Loong64F32x4Add)                   \
   V(Loong64F32x4Sub)                   \
   V(Loong64F32x4Mul)                   \

diff --git a/src/compiler/backend/loong64/instruction-selector-loong64.cc b/src/compiler/backend/loong64/instruction-selector-loong64.cc
@@ -2669,8 +2669,6 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
   V(F32x4Abs, kLoong64F32x4Abs)                               \
   V(F32x4Neg, kLoong64F32x4Neg)                               \
   V(F32x4Sqrt, kLoong64F32x4Sqrt)                             \
-  V(F32x4RecipApprox, kLoong64F32x4RecipApprox)               \
-  V(F32x4RecipSqrtApprox, kLoong64F32x4RecipSqrtApprox)       \
   V(F32x4Ceil, kLoong64F32x4Ceil)                             \
   V(F32x4Floor, kLoong64F32x4Floor)                           \
   V(F32x4Trunc, kLoong64F32x4Trunc)                           \

diff --git a/src/compiler/backend/mips/code-generator-mips.cc b/src/compiler/backend/mips/code-generator-mips.cc
@@ -2495,16 +2495,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       __ fsqrt_w(i.OutputSimd128Register(), i.InputSimd128Register(0));
       break;
     }
-    case kMipsF32x4RecipApprox: {
-      CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
-      __ frcp_w(i.OutputSimd128Register(), i.InputSimd128Register(0));
-      break;
-    }
-    case kMipsF32x4RecipSqrtApprox: {
-      CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
-      __ frsqrt_w(i.OutputSimd128Register(), i.InputSimd128Register(0));
-      break;
-    }
     case kMipsF32x4Add: {
       CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
       __ fadd_w(i.OutputSimd128Register(), i.InputSimd128Register(0),

diff --git a/src/compiler/backend/mips/instruction-codes-mips.h b/src/compiler/backend/mips/instruction-codes-mips.h
@@ -206,8 +206,6 @@ namespace compiler {
   V(MipsF32x4Abs)                  \
   V(MipsF32x4Neg)                  \
   V(MipsF32x4Sqrt)                 \
-  V(MipsF32x4RecipApprox)          \
-  V(MipsF32x4RecipSqrtApprox)      \
   V(MipsF32x4Add)                  \
   V(MipsF32x4Sub)                  \
   V(MipsF32x4Mul)                  \

diff --git a/src/compiler/backend/mips/instruction-scheduler-mips.cc b/src/compiler/backend/mips/instruction-scheduler-mips.cc
@@ -100,8 +100,6 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kMipsF32x4Ne:
     case kMipsF32x4Neg:
     case kMipsF32x4Sqrt:
-    case kMipsF32x4RecipApprox:
-    case kMipsF32x4RecipSqrtApprox:
     case kMipsF32x4ReplaceLane:
     case kMipsF32x4SConvertI32x4:
     case kMipsF32x4Splat:

diff --git a/src/compiler/backend/mips/instruction-selector-mips.cc b/src/compiler/backend/mips/instruction-selector-mips.cc
@@ -2154,8 +2154,6 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
   V(F32x4Abs, kMipsF32x4Abs)                                   \
   V(F32x4Neg, kMipsF32x4Neg)                                   \
   V(F32x4Sqrt, kMipsF32x4Sqrt)                                 \
-  V(F32x4RecipApprox, kMipsF32x4RecipApprox)                   \
-  V(F32x4RecipSqrtApprox, kMipsF32x4RecipSqrtApprox)           \
   V(F32x4Ceil, kMipsF32x4Ceil)                                 \
   V(F32x4Floor, kMipsF32x4Floor)                               \
   V(F32x4Trunc, kMipsF32x4Trunc)                               \

diff --git a/src/compiler/backend/mips64/code-generator-mips64.cc b/src/compiler/backend/mips64/code-generator-mips64.cc
@@ -2606,16 +2606,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       __ bnegi_w(i.OutputSimd128Register(), i.InputSimd128Register(0), 31);
       break;
     }
-    case kMips64F32x4RecipApprox: {
-      CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
-      __ frcp_w(i.OutputSimd128Register(), i.InputSimd128Register(0));
-      break;
-    }
-    case kMips64F32x4RecipSqrtApprox: {
-      CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
-      __ frsqrt_w(i.OutputSimd128Register(), i.InputSimd128Register(0));
-      break;
-    }
     case kMips64F32x4Add: {
       CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
       __ fadd_w(i.OutputSimd128Register(), i.InputSimd128Register(0),

diff --git a/src/compiler/backend/mips64/instruction-codes-mips64.h b/src/compiler/backend/mips64/instruction-codes-mips64.h
@@ -239,8 +239,6 @@ namespace compiler {
   V(Mips64F32x4Abs)                   \
   V(Mips64F32x4Neg)                   \
   V(Mips64F32x4Sqrt)                  \
-  V(Mips64F32x4RecipApprox)           \
-  V(Mips64F32x4RecipSqrtApprox)       \
   V(Mips64F32x4Add)                   \
   V(Mips64F32x4Sub)                   \
   V(Mips64F32x4Mul)                   \

diff --git a/src/compiler/backend/mips64/instruction-scheduler-mips64.cc b/src/compiler/backend/mips64/instruction-scheduler-mips64.cc
@@ -127,8 +127,6 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kMips64F32x4Ne:
     case kMips64F32x4Neg:
     case kMips64F32x4Sqrt:
-    case kMips64F32x4RecipApprox:
-    case kMips64F32x4RecipSqrtApprox:
     case kMips64F32x4ReplaceLane:
     case kMips64F32x4SConvertI32x4:
     case kMips64F32x4Splat:

diff --git a/src/compiler/backend/mips64/instruction-selector-mips64.cc b/src/compiler/backend/mips64/instruction-selector-mips64.cc
@@ -2911,8 +2911,6 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
   V(F32x4Abs, kMips64F32x4Abs)                               \
   V(F32x4Neg, kMips64F32x4Neg)                               \
   V(F32x4Sqrt, kMips64F32x4Sqrt)                             \
-  V(F32x4RecipApprox, kMips64F32x4RecipApprox)               \
-  V(F32x4RecipSqrtApprox, kMips64F32x4RecipSqrtApprox)       \
   V(F32x4Ceil, kMips64F32x4Ceil)                             \
   V(F32x4Floor, kMips64F32x4Floor)                           \
   V(F32x4Trunc, kMips64F32x4Trunc)                           \

diff --git a/src/compiler/backend/ppc/code-generator-ppc.cc b/src/compiler/backend/ppc/code-generator-ppc.cc
@@ -2833,14 +2833,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       __ xvnegsp(i.OutputSimd128Register(), i.InputSimd128Register(0));
       break;
     }
-    case kPPC_F32x4RecipApprox: {
-      __ xvresp(i.OutputSimd128Register(), i.InputSimd128Register(0));
-      break;
-    }
-    case kPPC_F32x4RecipSqrtApprox: {
-      __ xvrsqrtesp(i.OutputSimd128Register(), i.InputSimd128Register(0));
-      break;
-    }
     case kPPC_F32x4Sqrt: {
       __ xvsqrtsp(i.OutputSimd128Register(), i.InputSimd128Register(0));
       break;

diff --git a/src/compiler/backend/ppc/instruction-codes-ppc.h b/src/compiler/backend/ppc/instruction-codes-ppc.h
@@ -225,8 +225,6 @@ namespace compiler {
   V(PPC_F32x4Le)                     \
   V(PPC_F32x4Abs)                    \
   V(PPC_F32x4Neg)                    \
-  V(PPC_F32x4RecipApprox)            \
-  V(PPC_F32x4RecipSqrtApprox)        \
   V(PPC_F32x4Sqrt)                   \
   V(PPC_F32x4SConvertI32x4)          \
   V(PPC_F32x4UConvertI32x4)          \

diff --git a/src/compiler/backend/ppc/instruction-scheduler-ppc.cc b/src/compiler/backend/ppc/instruction-scheduler-ppc.cc
@@ -150,8 +150,6 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kPPC_F32x4Le:
     case kPPC_F32x4Abs:
     case kPPC_F32x4Neg:
-    case kPPC_F32x4RecipApprox:
-    case kPPC_F32x4RecipSqrtApprox:
     case kPPC_F32x4Sqrt:
     case kPPC_F32x4SConvertI32x4:
     case kPPC_F32x4UConvertI32x4:

diff --git a/src/compiler/backend/ppc/instruction-selector-ppc.cc b/src/compiler/backend/ppc/instruction-selector-ppc.cc
@@ -2325,8 +2325,6 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
   V(F64x2PromoteLowF32x4)      \
   V(F32x4Abs)                  \
   V(F32x4Neg)                  \
-  V(F32x4RecipApprox)          \
-  V(F32x4RecipSqrtApprox)      \
   V(F32x4Sqrt)                 \
   V(F32x4SConvertI32x4)        \
   V(F32x4UConvertI32x4)        \

diff --git a/src/compiler/backend/riscv64/code-generator-riscv64.cc b/src/compiler/backend/riscv64/code-generator-riscv64.cc
@@ -3175,16 +3175,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       __ vmv_vv(i.OutputSimd128Register(), kSimd128ScratchReg);
       break;
     }
-    case kRiscvF32x4RecipApprox: {
-      __ VU.set(kScratchReg, E32, m1);
-      __ vfrec7_v(i.OutputSimd128Register(), i.InputSimd128Register(0));
-      break;
-    }
-    case kRiscvF32x4RecipSqrtApprox: {
-      __ VU.set(kScratchReg, E32, m1);
-      __ vfrsqrt7_v(i.OutputSimd128Register(), i.InputSimd128Register(0));
-      break;
-    }
     case kRiscvF32x4Qfma: {
       __ VU.set(kScratchReg, E32, m1);
       __ vfmadd_vv(i.InputSimd128Register(1), i.InputSimd128Register(2),

diff --git a/src/compiler/backend/riscv64/instruction-codes-riscv64.h b/src/compiler/backend/riscv64/instruction-codes-riscv64.h
@@ -235,8 +235,6 @@ namespace compiler {
   V(RiscvF32x4Abs)                          \
   V(RiscvF32x4Neg)                          \
   V(RiscvF32x4Sqrt)                         \
-  V(RiscvF32x4RecipApprox)                  \
-  V(RiscvF32x4RecipSqrtApprox)              \
   V(RiscvF32x4Qfma)                         \
   V(RiscvF32x4Qfms)                         \
   V(RiscvF64x2Qfma)                         \

diff --git a/src/compiler/backend/riscv64/instruction-scheduler-riscv64.cc b/src/compiler/backend/riscv64/instruction-scheduler-riscv64.cc
@@ -119,8 +119,6 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kRiscvF32x4Ne:
     case kRiscvF32x4Neg:
     case kRiscvF32x4Sqrt:
-    case kRiscvF32x4RecipApprox:
-    case kRiscvF32x4RecipSqrtApprox:
     case kRiscvF64x2Qfma:
     case kRiscvF64x2Qfms:
     case kRiscvF32x4Qfma:

diff --git a/src/compiler/backend/riscv64/instruction-selector-riscv64.cc b/src/compiler/backend/riscv64/instruction-selector-riscv64.cc
@@ -2877,8 +2877,6 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
   V(F32x4Abs, kRiscvF32x4Abs)                                   \
   V(F32x4Neg, kRiscvF32x4Neg)                                   \
   V(F32x4Sqrt, kRiscvF32x4Sqrt)                                 \
-  V(F32x4RecipApprox, kRiscvF32x4RecipApprox)                   \
-  V(F32x4RecipSqrtApprox, kRiscvF32x4RecipSqrtApprox)           \
   V(F32x4DemoteF64x2Zero, kRiscvF32x4DemoteF64x2Zero)           \
   V(F32x4Ceil, kRiscvF32x4Ceil)                                 \
   V(F32x4Floor, kRiscvF32x4Floor)                               \

diff --git a/src/compiler/backend/s390/code-generator-s390.cc b/src/compiler/backend/s390/code-generator-s390.cc
@@ -2872,27 +2872,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       __ I8x16GeU(i.OutputSimd128Register(), i.InputSimd128Register(0),
                   i.InputSimd128Register(1), kScratchDoubleReg);
       break;
-    }
-      // vector unary ops
-    case kS390_F32x4RecipApprox: {
-      __ mov(kScratchReg, Operand(1));
-      __ ConvertIntToFloat(kScratchDoubleReg, kScratchReg);
-      __ vrep(kScratchDoubleReg, kScratchDoubleReg, Operand(0), Condition(2));
-      __ vfd(i.OutputSimd128Register(), kScratchDoubleReg,
-             i.InputSimd128Register(0), Condition(0), Condition(0),
-             Condition(2));
-      break;
-    }
-    case kS390_F32x4RecipSqrtApprox: {
-      Simd128Register dst = i.OutputSimd128Register();
-      __ vfsq(dst, i.InputSimd128Register(0), Condition(0), Condition(0),
-              Condition(2));
-      __ mov(kScratchReg, Operand(1));
-      __ ConvertIntToFloat(kScratchDoubleReg, kScratchReg);
-      __ vrep(kScratchDoubleReg, kScratchDoubleReg, Operand(0), Condition(2));
-      __ vfd(dst, kScratchDoubleReg, dst, Condition(0), Condition(0),
-             Condition(2));
-      break;
     }
     // vector boolean unops
     case kS390_V128AnyTrue: {

diff --git a/src/compiler/backend/s390/instruction-codes-s390.h b/src/compiler/backend/s390/instruction-codes-s390.h
@@ -208,8 +208,6 @@ namespace compiler {
   V(S390_F32x4Le)                           \
   V(S390_F32x4Abs)                          \
   V(S390_F32x4Neg)                          \
-  V(S390_F32x4RecipApprox)                  \
-  V(S390_F32x4RecipSqrtApprox)              \
   V(S390_F32x4SConvertI32x4)                \
   V(S390_F32x4UConvertI32x4)                \
   V(S390_F32x4Sqrt)                         \

diff --git a/src/compiler/backend/s390/instruction-scheduler-s390.cc b/src/compiler/backend/s390/instruction-scheduler-s390.cc
@@ -174,8 +174,6 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kS390_F32x4Le:
     case kS390_F32x4Abs:
     case kS390_F32x4Neg:
-    case kS390_F32x4RecipApprox:
-    case kS390_F32x4RecipSqrtApprox:
     case kS390_F32x4SConvertI32x4:
     case kS390_F32x4UConvertI32x4:
     case kS390_F32x4Sqrt:

diff --git a/src/compiler/backend/s390/instruction-selector-s390.cc b/src/compiler/backend/s390/instruction-selector-s390.cc
@@ -2548,8 +2548,6 @@ void InstructionSelector::VisitWord64AtomicStore(Node* node) {
   V(F64x2Splat)              \
   V(F32x4Abs)                \
   V(F32x4Neg)                \
-  V(F32x4RecipApprox)        \
-  V(F32x4RecipSqrtApprox)    \
   V(F32x4Sqrt)               \
   V(F32x4Ceil)               \
   V(F32x4Floor)              \

diff --git a/src/compiler/backend/x64/code-generator-x64.cc b/src/compiler/backend/x64/code-generator-x64.cc
@@ -2924,14 +2924,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       __ Sqrtps(i.OutputSimd128Register(), i.InputSimd128Register(0));
       break;
     }
-    case kX64F32x4RecipApprox: {
-      __ Rcpps(i.OutputSimd128Register(), i.InputSimd128Register(0));
-      break;
-    }
-    case kX64F32x4RecipSqrtApprox: {
-      __ Rsqrtps(i.OutputSimd128Register(), i.InputSimd128Register(0));
-      break;
-    }
     case kX64F32x4Add: {
       ASSEMBLE_SIMD_BINOP(addps);
       break;