Vivado Project: ASCII to Binary Converter

Description

This Vivado project implements a ASCII input of digits of legth 1 to 8 and giver result to binary output.

Prerequisites

• Xilinx Vivado (version 2018 or higher)
• FPGA board SP701 (optional for hardware testing)

Project Generation

1. Open Xilinx Vivado.
2. Goto TCL comandline.
3. CD to the repo directory
4. source ./create_project.tcl
5. the script will Run synthesis and implementation and Generate the bitstream.

References

The BCD conversion algorithem is inspired by below reference https://www.sciencedirect.com/science/article/pii/S0141933113000136?ref=pdf_download&fr=RR-2&rr=7f354380ab2c3e47