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Welcome to the robin wiki!

Basically this is a rolling list of plans for the SoC that I am implementing on an iCEbreaker board.

The CPU design is being documented on its own webpage

• optimizations in the cpu: less complex state machine and tighter read cycle. Those ideas will surface on the CPU Page
• nitpick source files with iverilog [because yosys is very lenient]
• implement a small fixed point math library to get a feel for code density and speed. This also doubles as a regression test framework to check changes in the cpu.
• memory mapped access to leds,buttons and perhaps gpio [leds done]
• Reset button, with proper debouncing [done Blog article]
• halt and reset vectors on the cpu
• assembler for the new cpu [mostly done, but undocumented]
• better/bigger memory system [added spram Blog article on spram]
• Memory mapped serial I/O [done mostly, but undocumented]
• CPU, with ALU [done mostly, but undocumented]
• UART, with FIFOs [done]
• UART, basic echoing [done Blog article]