Practice Verilog and SystemVerilog on our playground:

1. Write some code
2. Click Run
3. Check the logs
4. Success! Interact with the simulator!

Website: https://verilog-playground.github.io

Back-end: infrastructure

Front-end: verilog-playground.github.io

The front-end uses React and was created using create-react-app. It is hosted on GitHub Pages.

The back-end infrastructure is hosted on Amazon Web Services (AWS) and primarily consists of API Gateway and Lambda functions. The system is managed using the AWS Cloud Development Kit (CDK), which is an Infrastructure as Code (IaC) framework.

The simulation itself runs client-side. After the user submits the code, a Lambda function is triggered by API Gateway to start the transpilation process. This process first converts the Verilog/SystemVerilog code to C++ using Verilator, and then converts the C++ code to JavaScript using Emscripten. With the resulting JavaScript code in hand, the browser uses the eval function to interact with the simulation. The user receives logs about the process in real time, thanks to a WebSocket connection between the browser and the API Gateway.

• Scalable Web-Based FPGA Board simulator

• Many thanks to my professors Elmar Melcher and Joseana Fechine for their support and incentive since the beginning of the project.
• Many thanks to the Verilator and Emscripten developers for making it possible to run the simulation client-side, thereby enabling the creation of this project.