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Welcome to Verilog-to-Routing's documentation! Indices and tables
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Welcome to Verilog-to-Routing's documentation!

https://www.verilogtorouting.org/img/des90_placement_macros.gif

https://www.verilogtorouting.org/img/des90_nets.gif

https://www.verilogtorouting.org/img/des90_routing_util.gif

For more information on the Verilog-to-Routing (VTR) project see :ref:`vtr` and :ref:`vtr_cad_flow`.

For documentation and tutorials on the FPGA architecture description language see: :ref:`fpga_architecture_description`.

For more specific documentation about VPR see :ref:`vpr`.

.. toctree::
   :maxdepth: 2
   :caption: Quick Start

   quickstart/index


.. toctree::
   :maxdepth: 2
   :caption: Usage

   vtr/index
   arch/index
   vpr/index
   parmys/index
   odin/index
   abc/index
   tutorials/index
   utils/index


.. toctree::
   :maxdepth: 2
   :caption: Development

   dev/index
   CHANGELOG


.. toctree::
   :maxdepth: 2
   :caption: Appendix

   contact
   glossary
   zreferences


.. toctree::
   :maxdepth: 2
   :caption: API Reference

   api/vpr/index
   api/vtrutil/index
   api/vprinternals/index

Indices and tables