C Verilog C++ HTML Perl Python Other
Failed to load latest commit information.
.github Remove .github/README.md Jul 22, 2017
BROKEN_ENV/alpine switch name to something more appropriate Aug 3, 2017
ODIN_II Adding test/verification files for ansi style port declaration (#244) Nov 19, 2017
abc_with_bb_support Fix typo Jun 23, 2017
ace2 Fix checking of ACE warning suppression flags Jun 23, 2017
blifexplorer Fixed blifexplorer build dependencies. Oct 20, 2015
cmake Allow MinGW compilers to be overridden when cross-compiling for Windows Jun 21, 2017
dev_tools Add git bisect run script Jul 30, 2017
doc doc: Fix some missing/incorrect references Sep 22, 2017
libs vtrutil: Add vtr::vector class Nov 9, 2017
tutorial Checking buildbot valgrind parsing Jul 5, 2016
verilog_preprocessor modified arithmetic-related c++ code to compile with the partial impl… Sep 8, 2014
vpr vpr: Fix graphics by ensuring device grid initialized before graphics Nov 24, 2017
vtr_flow flow: Check that requested RR graph file was generated Nov 20, 2017
.gitignore Remove old gitignore patterns Oct 31, 2017
BUILDING.md Pull changes from master - test Jul 18, 2017
CMakeLists.txt Add Catch unit testing framework Nov 1, 2017
DOCKER_DEPLOY.md changes to the dockerfile Jul 6, 2017
Dockerfile Update Dockerfile Oct 23, 2017
LICENSE.md Clarify library licensing Oct 31, 2017
Makefile Add Catch unit testing framework Nov 1, 2017
README.developers.md fix strcmp and move developper relative instruction Jul 6, 2017
README.md Update Contributors Section in README.md Jul 26, 2017
Running_On_ARM(raspberry_pi).txt Update Running_On_ARM(raspberry_pi).txt Jul 27, 2017
run_quick_test.pl Remove legacy quick_test; use the standard regression testing infrast… Mar 23, 2017
run_reg_test.pl Revert "added a strcmp inside @vtr_util to do NULL check first(undefi… Jul 6, 2017
sweep_build_configs.py Add support for testing MinGW cross-compilation to Windows Jun 21, 2017



The Verilog-to-Routing (VTR) project is a world-wide collaborative effort to provide a open-source framework for conducting FPGA architecture and CAD research and development. The VTR design flow takes as input a Verilog description of a digital circuit, and a description of the target FPGA architecture. It then perfoms:

  • Elaboration & Synthesis (ODIN II)
  • Logic Optimization & Technology Mapping (ABC)
  • Packing, Placement, Routing & Timing Analysis (VPR)

to generate FPGA speed and area results. VTR also includes a set of benchmark designs known to work with the design flow.


Generally most code is under MIT license, with the exception of ABC which is distributed under its own (permissive) terms. Full license details can be found here.


For most users of VTR (rather than active developers) you should download the latest packaged (and regression tested) version of VTR from here.


On unix-like systems run make from the root VTR directory.

For more details see here.

Docker Cloud9 Deployment

We provide a Dockerfile that sets up all the necessary packages for VTR to run. Also, the Dockerfile sets up Cloud9, a workspace management system that runs on your browser and allows you to run (and modify) VTR remotely.

For more details see here.


VTR's full documentation is available here.

Mailing Lists

If you have questions, or want to keep up-to-date with VTR, consider joining our mailing lists:

VTR-Announce: VTR release announcements (low traffic)

VTR-Users: Discussions about using VTR

VTR-Devel: Discussions about VTR development

VTR-Commits: VTR revision control commits

How to Cite

The following paper may be used as a general citation for VTR:

J. Luu, J. Goeders, M. Wainberg, A. Somerville, T. Yu, K. Nasartschuk, M. Nasr, S. Wang, T. Liu, N. Ahmed, K. B. Kent, J. Anderson, J. Rose and V. Betz "VTR 7.0: Next Generation Architecture and CAD System for FPGAs," ACM TRETS, Vol. 7, No. 2, June 2014, pp. 6:1 - 6:30.


  title={{VTR 7.0: Next Generation Architecture and CAD System for FPGAs}},
  author={Luu, Jason and Goeders, Jeff and Wainberg, Michael and Somerville, Andrew and Yu, Thien and Nasartschuk, Konstantin and Nasr, Miad and Wang, Sen and Liu, Tim and Ahmed, Norrudin and Kent, Kenneth B. and Anderson, Jason and Rose, Jonathan and Betz, Vaughn},
  journal = {ACM Trans. Reconfigurable Technol. Syst.},


This is the development trunk for the Verilog-to-Routing project. Unlike the nicely packaged releases that we create, you are working with code in a constant state of flux. You should expect that the tools are not always stable and that more work is needed to get the flow to run.

For new developers, please do the tutorial in tutorial/NewDeveloperTutorial.txt. You will be directed back here once you ramp up.

VTR development follows a classic centralized repository (svn-like) workflow. The 'master' branch is supposed to be the most current stable version of the project. Developers checkout a local copy of the code at the start of development, then do regular updates (e.g. git pull) to keep in sync with the GitHub master. When a developer has a tested, working change to put back into the trunk, he/she performs a git push operation. Unstable code should remain in the developer's local copy.

We do automated testing of the trunk using BuildBot to verify functionality and Quality of Results (QoR).

IMPORTANT: A broken build must be fixed at top priority. You break the build if your commit breaks any of the automated regression tests.

For additional information see the developer README.


Please keep this up-to-date

Professors: Kenneth Kent, Vaughn Betz, Jonathan Rose, Jason Anderson, Peter Jamieson

Research Assistants: Aaron Graham

Graduate Students: Kevin Murray, Jason Luu, Oleg Petelin, Jeffrey Goeders, Chi Wai Yu, Andrew Somerville, Ian Kuon, Alexander Marquardt, Andy Ye, Wei Mark Fang, Tim Liu, Charles Chiasson, Panagiotis (Panos) Patros

Summer Students: Opal Densmore, Ted Campbell, Cong Wang, Peter Milankov, Scott Whitty, Michael Wainberg, Suya Liu, Miad Nasr, Nooruddin Ahmed, Thien Yu, Long Yu Wang, Matthew J.P. Walker, Amer Hesson, Sheng Zhong, Hanqing Zeng, Vidya Sankaranarayanan, Jia Min Wang, Eugene Sha, Jean-Philippe Legault

Companies: Altera Corporation, Texas Instruments