The Verilog-to-Routing (VTR) project luu_vtr,luu_vtr_7 is a world-wide collaborative effort to provide a open-source framework for conducting FPGA architecture and CAD research and development. The VTR design flow takes as input a Verilog description of a digital circuit, and a description of the target FPGA architecture.
It then perfoms:
- Elaboration & Synthesis (
odin_II)- Logic Optimization & Technology Mapping (
abc)- Packing, Placement, Routing & Timing Analysis (
vpr)
Generating FPGA speed and area results.
VTR also includes a set of benchmark designs known to work with the design flow.
get_vtr install_vtr cad_flow running_vtr benchmarks power_estimation/index.rst tasks run_vtr_flow run_vtr_task parse_vtr_flow parse_vtr_task parse_config pass_requirements