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Clean up get_rr_node_index a bit #355

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vaughnbetz opened this issue Jun 7, 2018 · 1 comment
Open

Clean up get_rr_node_index a bit #355

vaughnbetz opened this issue Jun 7, 2018 · 1 comment
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enhancement Feature enhancement VPR VPR FPGA Placement & Routing Tool

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@vaughnbetz
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get_rr_node_index has some odd code that should be cleaned up.

  1. For rr_node index lookups of CHANX types, the x and y index is swapped when rr_node_indices is loaded:

https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vpr/src/route/rr_graph2.cpp#L1255,L1264

Then when the lookup is done in get_rr_node_index, the indices are swapped again.

https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vpr/src/route/rr_graph2.cpp#L1354,L1356

We should stop doing that, and delete the comment about it.

  1. We allow lookups by side for CHANX and CHANY, even though side makes no sense for them. We should at least always go to side 0, rather than the enumerated type at sides[0] as that will break if sides[0] is not equal to 0.

https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vpr/src/route/rr_graph2.cpp#L1338,L1341

Proposed Behaviour

Same as current, but less confusing code under the hood.

Current Behaviour

None.

Possible Solution

See above.

Context

Code cleanup.

@vaughnbetz vaughnbetz added enhancement Feature enhancement VPR VPR FPGA Placement & Routing Tool labels Jun 7, 2018
@vaughnbetz
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@kmurray

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Labels
enhancement Feature enhancement VPR VPR FPGA Placement & Routing Tool
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